#ifndef __DDR_CTRL_H__
#define __DDR_CTRL_H__

#include "hme_conf.h"

#ifdef HME_P3

typedef struct {
    
    union {
        __IOM uint32_t reg_0x000;
        struct {
            __IOM uint32_t reg_ddrc_mem_choose : 3;                    /* bit[2,0].  Choose memory type that the controller needs to support:
                                                                * 000:DDR2
                                                                * 010:DDR3
                                                                * 100:DDR4
                                                                * 001:LPDDR2
                                                                * 011:LPDDR3
                                                                * 101:LPDDR4
                                                                * 111:LPDDR5
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_start : 1;                    /* bit[3].  The sdram initialization enable signal. Active High.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_phy_init_start : 1;                    /* bit[4].  The phy initialization enable signal. Active High.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_skip_init_start : 1;                    /* bit[5].  The enable signal to skip the sdram initial flow. Active High.
                                                                * 1: The controller will skip the sdram initial flow and set the core to the sdram initial complete state. Used in the LPDDR4 PHY command bus training mode.
                                                                * 0: Keep the current state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_disable_imc_if : 1;                    /* bit[6].  The register used to disable the core to accept the command from the slave interface. Active High.
                                                                * There are two mechanisms to make to core to stop to accept the command from the slave interface:
                                                                * 1) When the core_pd_entry or core_srf_entry is high.
                                                                * 2) When reg_disable_imc_if_syn is high. 
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_sdram_burst_length : 2;                    /* bit[8,7].  The register used to choose  the burst length that the controller needs to support.
                                                                * 2'b01: Burst 8
                                                                * 2'b10: Burst 16.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_sdram_dq_width : 2;                    /* bit[10,9].  The register use to choose the DQ width that the controller needs to support.
                                                                * 2'b00: DQ8
                                                                * 2'b01: DQ16
                                                                * 2'b10: DQ32
                                                                * 2'b11: DQ64
                                                                * Default Vale : 0x2  */
            __IOM uint32_t reg_ctrl_ddrc_clk_disable : 1;                    /* bit[11].  Used to control the dfi_dram_clk_disable sigle of the dfi interface.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_out_of_order_dis : 1;                    /* bit[12].  Disable the out of order function of the read channel. Active High.
                                                                * 1: Disable the out of function of the read channel. The read back data will accord to the order that the read commands appear on the AXI read address channel. The rid will have the same order with the arid.
                                                                * 0: Enable the out of function of the read channel. The read back data which comes back early will send to the axi read data interface early. The slave will keep the order of the same id but random order for different id.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_2t_mode : 1;                    /* bit[13].  The enable signal of the 2T mode for DDR3/DDR4. Acitvie High.
                                                                * This bit only can set to 1'b1 when the controller chooses the DDR3/DDR4 mode.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_aclk_cg_en : 1;                    /* bit[14].  Enable axi clock gate in low power mode
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_ddrc_core_clock_gate_en : 1;                    /* bit[15].  The clock gate enable signal of the core.
                                                                * 1: When there is no pending write operation, read operation and all read data has already back. The unused logic will be keep the current state and go to the clock gating state.
                                                                * 0: Disable the clock gate function.
                                                                * Default Vale : 0x0  */
                uint32_t  : 1;
            __IOM uint32_t reg_ddrc_gear_down_mode : 1;                    /* bit[17].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_auto_ref_pb_dis : 1;                    /* bit[18].  The enable signal of the auto refresh perbank function. Active Low.
                                                                * 0: The controller will use the auto refresh perbank to complete the auto-refresh operation of the SDRAM.
                                                                * 1: Disable this function.
                                                                * Default Vale : 0x1  */
                uint32_t  : 1;
            __IOM uint32_t reg_ddrc_sideband_ecc_en : 1;                    /* bit[20].  1:Enable the sideband ecc function. 
                                                                * 0:Disable the sideband ecc function.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_inline_ecc_en : 1;                    /* bit[21].  1:Enable the inline ecc function. 
                                                                * 0:Disable the inline ecc function.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_mem_bist_channel_en : 10;                    /* bit[31,22].  The byte enable signal of the MEM-BIST function. 
                                                                * [0]: The enable signal of the BYTE0.
                                                                * [1]: The enable signal of the BYTE1.
                                                                * [2]: The enable signal of the BYTE2.
                                                                * [3]: The enable signal of the BYTE3.
                                                                * [4]: The enable signal of the BYTE4.
                                                                * [5]: The enable signal of the BYTE5.
                                                                * [6]: The enable signal of the BYTE6.
                                                                * [7]: The enable signal of the BYTE7.
                                                                * [8]: The enable signal of the BYTE8.
                                                                * When choose the DQ72 mode, this register should set to 9'h1ff.
                                                                * When choose the DQ64 mode, this register should set to 8'hff.
                                                                * When choose the DQ32 mode, this register should set to 8'hf.
                                                                * When choose the DQ16 mode, this register should set to 8'h3. 
                                                                * When choose the DQ8 mode, this register should set to 8'h1.
                                                                * Default Vale : 0xff  */
        } reg_0x000_b;
    };

    union {
        __IOM uint32_t reg_0x004;
        struct {
            __IOM uint32_t reg_trp : 16;                    /* bit[15,0].  tRP: Indicates the minimum time from single-bank precharge to activate of same bank. Only can support the even delay.
                                                                * tRP = reg_trp * Tck
                                                                * Note: reg_trp >= 6.
                                                                * Note: The controller can only support the even number of Tck delay, even the reg_tpd is odd. The controller will ignore the bit[0].
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_trcd : 16;                    /* bit[31,16].  tRCD: Indicates the minimum time from activate to read or write command to same bank. 
                                                                * tRCD = {reg_trcd[7:1],1'b1}*Tck.
                                                                * Eg: When reg_trcd = 8'h4/8'h5, the tRCD = 5Tck. 
                                                                * Default Vale : 0xf  */
        } reg_0x004_b;
    };

    __IOM uint32_t reg_0x008;                /* Used to control the timing parameter of tRAS(MAX): The page need to be close after the tRAS time.
                                                                * tRAS=reg_tras * Tclk
                                                                * Default Vale : 0x3fff  */

    union {
        __IOM uint32_t reg_0x00c;
        struct {
            __IOM uint32_t reg_tras_min : 16;                    /* bit[15,0].  tRAS(min) - Specifies the minimum time between activate and precharge to the same bank.
                                                                * tRAS(min)= reg_tras_min*Tck
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_trc : 16;                    /* bit[31,16].  tRC - Specifies the minimum time between activates to same bank
                                                                * tRC = reg_trc* Tck
                                                                * Note: reg_trc >=6.
                                                                * Default Vale : 0xf  */
        } reg_0x00c_b;
    };

    union {
        __IOM uint32_t reg_0x010;
        struct {
            __IOM uint32_t reg_trrd_s : 16;                    /* bit[15,0].  tRRD_S: This is the minimum time between activates from bank "a" to bank "b" for different bank group.
                                                                * tRRD_S = reg_trrd_s *Tck 
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_trrd_l : 16;                    /* bit[31,16].  DDR4: tRRD_L: This is the minimum time between activates from bank "a" to bank "b" for same bank group.
                                                                * tRRD_L = reg_trrd_l *Tck 
                                                                * Default Vale : 0xf  */
        } reg_0x010_b;
    };

    union {
        __IOM uint32_t reg_0x014;
        struct {
            __IOM uint32_t reg_twtr_l : 8;                    /* bit[7,0].  tWTR_L: Internal write to read command delay for same bank group
                                                                * tWTR_L = reg_twtr_l *Tck
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_twtr_s : 8;                    /* bit[15,8].  tWTR_S: Internal write to read command delay for different bank group
                                                                * tWTR_S = reg_twtr_s *Tck
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_twr : 8;                    /* bit[23,16].  tWR: Write recovery time. Only can support the even delay.
                                                                * tWR = reg_twr *Tck
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_tfaw : 8;                    /* bit[31,24].  tFAW - valid only when 8 or more banks(or banks x bank groups) are present.In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles.
                                                                * tFAW= reg_tfaw*Tck
                                                                * Default Vale : 0xf  */
        } reg_0x014_b;
    };

    union {
        __IOM uint32_t reg_0x018;
        struct {
            __IOM uint32_t reg_tccd_l : 8;                    /* bit[7,0].  DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group.
                                                                * tCCD_L = reg_tccd_l *Tck
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_tccd_s : 8;                    /* bit[15,8].  For DDR3 mode, this parameter is used to control the timing delay between the Cas to Cas command delay of the same bank.
                                                                * For DDR4 mode, this parameter is used to control the timing delay between the Cas to CAS command delay of the different bank group.
                                                                * tCCD_S = reg_tccd_s *Tck 
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_trtp : 8;                    /* bit[23,16].  tRTP - Specifies the minimum time from read to precharge of same bank. Only can support the odd delay.
                                                                * tRTP = reg_trtp * Tck
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_trtw : 8;                    /* bit[31,24].  The register is used to control the delay between the read command to the write command.
                                                                * Default Vale : 0x0  */
        } reg_0x018_b;
    };

    union {
        __IOM uint32_t reg_0x01c;
        struct {
            __IOM uint32_t reg_ddrc_tmrr : 8;                    /* bit[7,0].  tMRR - Parameter used only in LPDDR4.Indicates the number of cycles between load mode read command and following valid command
                                                                * tMRR = reg_ddrc_tmrr *Tclk
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_tmrw : 8;                    /* bit[15,8].  tMRW - Parameter used only in DDR3 and DDR4.Indicates the number of cycles between load mode command and following load mode command
                                                                * tMRW = reg_ddrc_tmrw *Tclk
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_tmod : 8;                    /* bit[23,16].  tMOD - Parameter used only in DDR3 and DDR4.Indicates the number of cycles between load mode command and following non-load mode command
                                                                * tMOD = reg_ddrc_tmod *Tclk
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_tmrd : 8;                    /* bit[31,24].  tMRD- Indicates the number of cycles to wait after a mode register write or read
                                                                * tMRD = reg_drrc_tmrd *Tclk
                                                                * Default Vale : 0x0  */
        } reg_0x01c_b;
    };

    union {
        __IOM uint32_t reg_0x020;
        struct {
            __IOM uint32_t reg_ddrc_trefi_x32 : 13;                    /* bit[12,0].  Used to control the timing parameter of tREFI: The max timer between the auto refresh.
                                                                * In the idle conditional, the controller will generate the Auto-Refresh command according to the tREFI, but when the row is open at the same time, the controller needs to wait to close that pgae for tRAS_MIN which is controlled by the reg_tras_min. So when you configure this register, the user needs to provide some lead.
                                                                * eg: For 800Mbps of DDR3, when the tREFI is 7.8us. The reg_ddrc_t_refx_x32 = ((7800/2.5)>>1)/32-reg_tras_min.
                                                                * tREFI= reg_ddrc_t_refi_x32 *32*Tcore_clk
                                                                * Default Vale : 0x7f  */
            __IOM uint32_t reg_ddrc_trfc_min : 10;                    /* bit[22,13].  Used to control the timing parameter of tRFC: The minium timer form refresh to other commands.
                                                                * tRFC= reg_ddrc_t_rfc_min *Tck
                                                                * Default Vale : 0x11f  */
                uint32_t  : 9;
        } reg_0x020_b;
    };

    union {
        __IOM uint32_t reg_0x024;
        struct {
            __IOM uint32_t reg_ddrc_txpr : 12;                    /* bit[11,0].  The register related to the DDR4/DDR3 initialization. Used to control the timing parameter tXPR which means the gap when the dfi_cke changes to high to the following command.
                                                                * tXPR = reg_ddrc_txpr*Tclk
                                                                * Default Vale : 0x0  */
                uint32_t  : 4;
            __IOM uint32_t reg_tcke : 5;                    /* bit[20,16].  This register is used to control the timing parameter tCKE which means the minimum pulse width of the CKE.
                                                                * tCKE = reg_tcke * tCK.
                                                                * Note: The controller can only support the even number of Tck delay, even the reg_tpd is odd. The controller will ignore the bit[0].
                                                                * Default Vale : 0x5  */
                uint32_t  : 3;
            __IOM uint32_t reg_tpd : 5;                    /* bit[28,24].  The register is used to control the timing parameter tPD which means the Power Down Entry to Exit Timing.
                                                                * tPD = reg_tpd *Tclk.
                                                                * Default Vale : 0x5  */
                uint32_t  : 3;
        } reg_0x024_b;
    };

    union {
        __IOM uint32_t reg_0x028;
        struct {
            __IOM uint32_t reg_ddrc_trp : 8;                    /* bit[7,0].  This register is used to control the timing parameter tRP which means the timing between the precharge command to the active command for the same bank.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_ddrc_tdllk : 8;                    /* bit[15,8].  The register related to the initialization. Used to control the timing parameter tDLLK which means the timing between the last load mode command to the DES command after the ZQCL. 
                                                                * tDLLK = reg_ddrc_tdllk * Tclk.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_tppd : 8;                    /* bit[23,16].  The register is used to control the timing of the tPPD timing parameter when the Controller choose the LPDDR4 mode.
                                                                * This is the minimum time from precharge to precharge command.
                                                                * tPPD = reg_tppd * Tclk
                                                                * Default Vale : 0x4  */
            __IOM uint32_t reg_tccd_mw : 8;                    /* bit[31,24].  The register is used to control the timing parameter tCCDMW timing parameter when the Controller Choose the LPDDR4 mode.
                                                                * This is the minimum time from write or masked write to masked write command for same bank.
                                                                * tCCDMW = reg_tccd_mw*Tclk
                                                                * Default Vale : 0x20  */
        } reg_0x028_b;
    };

    union {
        __IOM uint32_t reg_0x02c;
        struct {
            __IOM uint32_t reg_ddrc_txp : 8;                    /* bit[7,0].  The register is used to control the gap between the powern exit command to next valid command.
                                                                * Delay Unit = tCK.
                                                                * Default Vale : 0x8  */
            __IOM uint32_t reg_ddrc_trpa : 8;                    /* bit[15,8].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_tescke : 4;                    /* bit[19,16].  The register is used to control the delay from self refresh command to CKE input low.
                                                                * Delay Unit = tCK.
                                                                * Default Vale : 0x0  */
                uint32_t  : 4;
            __IOM uint32_t reg_tckesr : 4;                    /* bit[27,24].  This register is used to control the timing parameters of tCKESR which means the minimum pulse of the CKE between the self-refrsh entry to self-refresh exit.
                                                                * tCKESR = reg_tckesr * Tck.
                                                                * Note: The controller can only support the even number of Tck delay, even the reg_tpd is odd. The controller will ignore the bit[0].
                                                                * Default Vale : 0x5  */
                uint32_t  : 4;
        } reg_0x02c_b;
    };

    union {
        __IOM uint32_t reg_0x030;
        struct {
            __IOM uint32_t reg_ddrc_tzqoper : 14;                    /* bit[13,0].  Normal operation Full calibration time. After the self-refresh operation, the controller will send the zacalib operation and wait for reg_ddrc_tzqoper to allower to generate the following load mode command when reg_ddrc_zqcal_after_sref_en = 1'b1.
                                                                * Default Vale : 0x200  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_txs : 14;                    /* bit[29,16].  The register is used to control the gap between the sref-refresh exit command to next valid command.
                                                                * Delay Unit = tCK.
                                                                * Note: The inno ddr controller will ignore the next valid command needs the DLL locked or not. The user should choose the max( txs,txsdll,txs_ABOUT,txs_fast). 
                                                                * Default Vale : 0x200  */
                uint32_t  : 2;
        } reg_0x030_b;
    };

    union {
        __IOM uint32_t reg_0x034;
        struct {
            __IOM uint32_t reg_twtrp : 8;                    /* bit[7,0].  Reserved.
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_trfcpb : 10;                    /* bit[17,8].  Reserved.
                                                                * Default Vale : 0xf  */
                uint32_t  : 14;
        } reg_0x034_b;
    };

    union {
        __IOM uint32_t reg_0x038;
        struct {
            __IOM uint32_t reg_ddrc_trd2mrr : 8;                    /* bit[7,0].  tRD2MRR:  This is the minimus time the read to mode register read operation.
                                                                * tRD2MRR = reg_ddrc_trd2mrr * Tck.
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_ddrc_tmrr2mrw : 8;                    /* bit[15,8].  tMRR2MRW:  This is the minimus time the mode register read to mode register write operation.
                                                                * tMRR2MRW = reg_ddrc_tmrr2mrw * Tck.
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_ddrc_tmrr2wr : 8;                    /* bit[23,16].  tMRR2WR:  This is the minimus time the mode register read to write operation.
                                                                * tMRR2WR = reg_ddrc_tmrr2wr * Tck.
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_ddrc_tmrr2rd : 8;                    /* bit[31,24].  tMRR2RD:  This is the minimus time the mode register read to read operation.
                                                                * tMRR2RD = reg_ddrc_tmrr2rd * Tck.
                                                                * Default Vale : 0xf  */
        } reg_0x038_b;
    };

    union {
        __IOM uint32_t reg_0x03c;
        struct {
            __IOM uint32_t reg_ddrc_tmrri : 8;                    /* bit[7,0].  Reserved.
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_ddrc_twr2mrw : 8;                    /* bit[15,8].  tWR2MRW:  This is the minimus time the write to mode register write operation.
                                                                * tWR2MRW = reg_ddrc_twr2mrw * Tck.
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_ddrc_trd2mrw : 8;                    /* bit[23,16].  tRD2MRW:  This is the minimus time the read to mode register write operation.
                                                                * tRD2MRW = reg_ddrc_trd2mrw * Tck.
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_ddrc_twr2mrr : 8;                    /* bit[31,24].  tWR2MRR:  This is the minimus time the write to mode register read operation.
                                                                * tWR2MRR = reg_ddrc_twr2mrr * Tck.
                                                                * Default Vale : 0xf  */
        } reg_0x03c_b;
    };

    union {
        __IOM uint32_t reg_0x040;
        struct {
            __IOM uint32_t reg_derated_trp : 16;                    /* bit[15,0].  tRP: Indicates the minimum time from single-bank precharge to activate of same bank. Only can support the even delay for lpddr4/5 derated mode.
                                                                * tRP = reg_derated_trp * Tck
                                                                * Note: reg_derated_trp >= 6.
                                                                * Note: The controller can only support the even number of Tck delay, even the reg_tpd is odd. The controller will ignore the bit[0].
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_derated_trcd : 16;                    /* bit[31,16].  tRCD: Indicates the minimum time from activate to read or write command to same bank for lpddr4/5 derated mode. 
                                                                * tRCD = {reg_derated_trcd[7:1],1'b1}*Tck.
                                                                * Eg: When reg_derated_trcd = 8'h4/8'h5, the tRCD = 5Tck. 
                                                                * Default Vale : 0xf  */
        } reg_0x040_b;
    };

    union {
        __IOM uint32_t reg_0x044;
        struct {
            __IOM uint32_t reg_derated_tras_min : 16;                    /* bit[15,0].  tRAS(min) - Specifies the minimum time between activate and precharge to the same bank for lpddr4/5 derated mode.
                                                                * tRAS(min)= reg_derated_tras_min*Tck
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_derated_trc : 16;                    /* bit[31,16].  tRC - Specifies the minimum time between activates to same bank for lpddr4/5 derated mode.
                                                                * tRC = reg_derated_trc* Tck
                                                                * Note: reg_trc >=6.
                                                                * Default Vale : 0xf  */
        } reg_0x044_b;
    };

    union {
        __IOM uint32_t reg_0x048;
        struct {
            __IOM uint32_t reg_derated_trrd_s : 16;                    /* bit[15,0].  tRRD_S: This is the minimum time between activates from bank "a" to bank "b" for different bank group for lpddr4/5 derated mode.
                                                                * tRRD_S = reg_derated_trrd_s *Tck 
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_derated_trrd_l : 16;                    /* bit[31,16].  DDR4/LPDDR5: tRRD_L: This is the minimum time between activates from bank "a" to bank "b" for same bank group for lpddr4/5 derated mode.
                                                                * tRRD_L = reg_derated_trrd_l *Tck 
                                                                * Default Vale : 0xf  */
        } reg_0x048_b;
    };

    union {
        __IOM uint32_t reg_0x04c;
        struct {
            __IOM uint32_t reg_ddrc_init_tzqinit : 11;                    /* bit[10,0].  The register related to the initialization. Used to control the timing parameter tzqinit which means the timing between the ZQCL to the following command. 
                                                                * tZQINIT = reg_ddrc_tzqinit * Tclk.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_treset_h_x1024 : 13;                    /* bit[23,11].  The register is related to the sdram initialization. It is used to control the timing that the dfi_resetn changes to high to the dfi_cke chagne to high when the controller is in sdram initialization state.
                                                                * For DDR3, it should keep at least 500us.  
                                                                * The delay = reg_ddrc_treset_h_x1024 * 1024 * Tclk.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_treset_l_x1024 : 8;                    /* bit[31,24].  The register is related to the sdram initialization. It is used to control the timing that the dfi_resetn should keep low when the controller is in sdram initialization state.
                                                                * For DDR3, it should keep at least 200us.  
                                                                * The delay = reg_ddrc_treset_l_x1024 * 1024 * Tclk.
                                                                * Default Vale : 0x0  */
        } reg_0x04c_b;
    };

    union {
        __IOM uint32_t reg_0x050;
        struct {
            __IOM uint32_t reg_init_lpddr23_pd_wait : 8;                    /* bit[7,0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_init_lpddr23_pd_entry : 8;                    /* bit[15,8].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_init_lpddr23_pd_exit : 8;                    /* bit[23,16].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddr23_tinit5 : 8;                    /* bit[31,24].  Reserved.
                                                                * Default Vale : 0x0  */
        } reg_0x050_b;
    };

    union {
        __IOM uint32_t reg_0x054;
        struct {
            __IOM uint32_t reg_lpddr23_load_mode_mrwzqcl : 16;                    /* bit[15,0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddr23_load_mode_mrwreset : 16;                    /* bit[31,16].  Reserved.
                                                                * Default Vale : 0x0  */
        } reg_0x054_b;
    };

    union {
        __IOM uint32_t reg_0x058;
        struct {
            __IOM uint32_t reg_lpddr23_load_mode_read : 16;                    /* bit[15,0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t timer_lpddr23_pd_exit_select : 2;                    /* bit[17,16].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t timer_lpddr23_pd_wait_select : 2;                    /* bit[19,18].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t timer_lpddr23_pd_entry_select : 2;                    /* bit[21,20].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddr23_preact_before_mrwreset : 1;                    /* bit[22].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddr23_preall_before_mrwreset : 1;                    /* bit[23].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_init_lpddr23_pd_en : 1;                    /* bit[24].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_init_lpddr23_mrr_en : 1;                    /* bit[25].  Reserved.
                                                                * Default Vale : 0x0  */
                uint32_t  : 6;
        } reg_0x058_b;
    };

    union {
        __IOM uint32_t reg_0x05c;
        struct {
            __IOM uint32_t reg_ddrc_init_bp_load_mode_value : 18;                    /* bit[17,0].  Reserved.
                                                                * Default Vale : 0x0  */
                uint32_t  : 6;
            __IOM uint32_t reg_ddrc_init_bp_load_mode_addr : 4;                    /* bit[27,24].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_rank_num : 4;                    /* bit[31,28].  Reserved.
                                                                * Default Vale : 0x0  */
        } reg_0x05c_b;
    };

    __IOM uint32_t reg_0x060;                /* Reserved.
                                                                * Default Vale : 0x0  */

    union {
        __IOM uint32_t reg_0x064;
        struct {
            __IOM uint32_t reg_ddrc_valid_rank_num : 4;                    /* bit[3,0].  Reserved.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_init_ddr34_mirror_en : 1;                    /* bit[4].  Reserved.
                                                                * Default Vale : 0x0  */
                uint32_t  : 27;
        } reg_0x064_b;
    };

    union {
        __IOM uint32_t reg_0x068;
        struct {
            __IOM uint32_t reg_ddrc_init_bp_en : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_rstn : 1;                    /* bit[1].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_cke : 1;                    /* bit[2].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_nop : 1;                    /* bit[3].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_load_mode : 1;                    /* bit[4].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_zqcl : 1;                    /* bit[5].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_refab : 1;                    /* bit[6].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_preall : 1;                    /* bit[7].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_done : 1;                    /* bit[8].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_mpc : 1;                    /* bit[9].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_cs_high : 1;                    /* bit[10].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_cs_low : 1;                    /* bit[11].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_init_bp_zqlat : 1;                    /* bit[12].  Reserved.
                                                                * Default Vale : 0x0  */
                uint32_t  : 19;
        } reg_0x068_b;
    };

    union {
        __IOM uint32_t reg_0x06c;
        struct {
            __IOM uint32_t reg_vref_dq_init_en : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_vref_ca_init_en : 1;                    /* bit[1].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_cmd_zq_init_en : 1;                    /* bit[2].  Reserved.
                                                                * Default Vale : 0x0  */
                uint32_t  : 29;
        } reg_0x06c_b;
    };

    union {
        __IOM uint32_t reg_0x070;
        struct {
            __IOM uint32_t reg_ddrc_init_vref_dq : 16;                    /* bit[15,0].  Reserved.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_ddrc_init_vref_ca : 16;                    /* bit[31,16].  Reserved.
                                                                * Default Vale : 0x1  */
        } reg_0x070_b;
    };

    union {
        __IOM uint32_t reg_0x074;
        struct {
            __IOM uint32_t reg_ddrc_init_tckeh : 8;                    /* bit[7,0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_tinit1_100ns : 8;                    /* bit[15,8].  Used to contol the timing parameter of tinit1 100ns for lpddr23.
                                                                * Default Vale : 0x40  */
                uint32_t  : 8;
            __IOM uint32_t reg_ddrc_init_tzqlat : 8;                    /* bit[31,24].  Reserved.
                                                                * Default Vale : 0x0  */
        } reg_0x074_b;
    };

    union {
        __IOM uint32_t reg_0x078;
        struct {
            __IOM uint32_t reg_ddrc_txsr : 8;                    /* bit[7,0].  The reigster used to control the timing paramter tXSR: .Self refresh exit to next valid command delay. Only Used for LPDDR4. Please set to 0 for other sdram types.
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_ddrc_tsr : 8;                    /* bit[15,8].  The reigster used to control the timing paramter tSR: Minimum self refresh time (entry to exit). Only Used for LPDDR4. Please set to 0 for other sdram types.
                                                                * Default Vale : 0xf  */
                uint32_t  : 16;
        } reg_0x078_b;
    };

    union {
        __IOM uint32_t reg_0x07c;
        struct {
            __IOM uint32_t reg_slm_cmd_idle_cnt_x32_sref : 8;                    /* bit[7,0].  The idle numbers that will triger the controller to generate the self-refresh command when reg_srm_dis_auto_sref = 1'b0. 
                                                                * The idle_numbers = reg_srm_cmd_idle_cnt_x32_sref * 32.
                                                                * Default Vale : 0x40  */
            __IOM uint32_t reg_slm_cmd_idle_cnt_x32_ppd : 8;                    /* bit[15,8].  The idle numbers that will triger the controller to generate the precharge power down command when reg_srm_dis_auto_ppd = 1'b0. 
                                                                * The idle_numbers = reg_srm_cmd_idle_cnt_x32_pd * 32.
                                                                * Default Vale : 0x40  */
            __IOM uint32_t reg_slm_timeout_cnt_x1024_sref : 8;                    /* bit[23,16].  The register used to control the timeout value of the self-refrsh entry.
                                                                * time_unit: 1024*dfi_clk1x
                                                                * Default Vale : 0x40  */
            __IOM uint32_t reg_slm_timeout_cnt_x1024_ppd : 8;                    /* bit[31,24].  The register used to control the timeout value of the power down entry.
                                                                * time_unit: 1024*dfi_clk1x
                                                                * Default Vale : 0x40  */
        } reg_0x07c_b;
    };

    union {
        __IOM uint32_t reg_0x080;
        struct {
            __IOM uint32_t reg_slm_sref_req : 1;                    /* bit[0].  The request signal to use the controller to make the SDRAM go into the self-refresh state. Posedge is valid.
                                                                * When the controller detects this signal changes from low to high, it will stall the command go into the core of the controller from the slave interface and wait for all the command in the queue have been executed safety, then it will generate the slef-refresh command and send to the SDRAM.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_slm_ppd_req : 1;                    /* bit[1].  The request signal to use the controller to make the SDRAM go into the precharge power down state. Posedge is valid.
                                                                * When the controller detects this signal changes from low to high, it will stall the command go into the core of the controller from the slave interface and wait for all the command in the queue have been executed safety, then it will generate the power-down command and send to the SDRAM.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_slm_dis_auto_sref : 1;                    /* bit[2].  The disable signal of the auto generate self-refresh function. Active high.
                                                                * 0: Enable auto generate self-refresh function. After enable this function, the controller will monitor the idle state of the core, when the idle numbers arrive the number setting by the reg_srm_cmd_idle_cnt_x32_sref, the controller will generate the self-refresh command automatically.
                                                                * 1: Disable auto generate self-refresh function.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_slm_dis_auto_ppd : 1;                    /* bit[3].  The disable signal of the auto generate precharge power down function. Active high.
                                                                * 0: Enable auto generate precharge power down function. After enable this function, the controller will monitor the idle state of the core, when the idle numbers arrive the number setting by the reg_srm_cmd_idle_cnt_x32_pd, the controller will generate the precharge power downcommand automatically.
                                                                * 1: Disable auto generate precharge power down function.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_slm_sref_ppd_req : 1;                    /* bit[4].  The request signal to use the controller to make the SDRAM go into the self-refresh power down state.
                                                                * Default Vale : 0x0  */
                uint32_t  : 1;
            __IOM uint32_t reg_ddrc_dfilp_en : 1;                    /* bit[6].  The enable singal of the dfi low power function. When enable this function, the controller will use the dfi low power interface to make the PHY go into the low power state after it generates the self-refresh command.
                                                                * 1: Enable the dfi low power function when the controller goes into the low power flow.
                                                                * 0: Disable the dfi low power function.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_dfi_lp_state_clean : 1;                    /* bit[7].  The error staus( reg_dfi_lp_entry_handshake_fail and reg_dfi_lp_exit_handshake_timeout) clean signal. Active high.
                                                                * When this bit set to high, the error staus will be clean to zero then to lock the new staus of the dfi low power.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_dfilp2sref_gap : 8;                    /* bit[15,8].  The register is used to control the gap between the low dfi_lp_ack to sref-refresh exit command on the sdram pad.
                                                                * This register valid only when the reg_ddrc_dfilp_en = 1'b1.
                                                                * Delay Unit = tCK.
                                                                * Default Vale : 0x8  */
            __IOM uint32_t reg_ddrc_sref2dfilp_gap : 8;                    /* bit[23,16].  The register is used to control the gap between the sref-refresh enter command on the sdram pad to active the dfi_lp_req.
                                                                * This register valid only when the reg_ddrc_dfilp_en = 1'b1.
                                                                * Delay Unit = tCK.
                                                                * Default Vale : 0x8  */
            __IOM uint32_t reg_lpddr4_self_ppd_en : 1;                    /* bit[24].  The enable signal to enters the power down automatically after the controller completes the flow to enter self-refresh state for LPDDR4 Memory Mode. Active High.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_lpddrn_exit_ppd_at_self_refresh : 1;                    /* bit[25].  Only used for LPDDR4 Memory mode.When the reg_lpddr4_self_ppd_en set to 1, the controller will start to go into the power down after completing the flow the enter self-refresh state. When the user wants to exit the power down state using the register, after the controller completes the flow to exit the power down state to go back to the slef-refresh state, when this bit set to 0, the controller will keep the self-refresh state until this bit set to 1, then the controller will start the flow to exit the self-refresh state.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_ddrc_lpddrn_enter_ppd_at_self_refresh : 1;                    /* bit[26].  Only used for LPDDR4 Memory mode.When the reg_lpddr4_self_ppd_en set to 1, the controller will start to go into the power down after completing the flow the enter self-refresh state until this bit set to 1.
                                                                * So when this bit set to 0 at the initial state, when the controller complete the flow to enter self-refresh in the LPDDR4 Memory mode, it will keep in the self-refresh state. Then the user can complete the user load mode setting and set this bit to 1 to switch to the power down mode.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_ddrc_zqcal_after_sref_en : 1;                    /* bit[27].  The enable signal to generate the zqcali operation after the exit self-refresh operation. Active High.
                                                                * Default Vale : 0x1  */
                uint32_t  : 4;
        } reg_0x080_b;
    };

    union {
        __IOM uint32_t reg_0x084;
        struct {
            __IOM uint32_t reg_dfi_lp_wakeup_pd : 4;                    /* bit[3,0].  The register is used to conrol the dfi_lp_wakeup value of the dfi low power interface when the controller is deal with the low power request. When the controller goes into the low power of the precharge power down state and the reg_ddrc_dfilp_en = 1'b1, the controller will also use the dfi low power interface to make the phy goes into different low power state through the dfi_lp_wakeup. And the dfi_lp_wakeup will output the value setting by this register when assert the dfi_lp_req.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_dfi_lp_wakeup_sref : 4;                    /* bit[7,4].  The register is used to conrol the dfi_lp_wakeup value of the dfi low power interface when the controller is deal with the low power request. When the controller goes into the low power of the self-refresh state and the reg_ddrc_dfilp_en = 1'b1, the controller will also use the dfi low power interface to make the phy goes into different low power state through the dfi_lp_wakeup. And the dfi_lp_wakeup will output the value setting by this register when assert the dfi_lp_req.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_dfi_lp_entry_wait_time : 8;                    /* bit[15,8].  The register is used to set the waiting time of the assert of the dfi_lp_ack after the controller assert the dfi_lp_req. The delay unit is core_clk. When the controller can't wait for the assert of the dfi_lp_ack, the reg_dfi_lp_entry_handshake signal will change to high and keep to 1'b1 until to the next dfi low power operation.
                                                                * Default Vale : 0x9  */
            __IOM uint32_t reg_ddrc_pd2dfilp_gap : 8;                    /* bit[23,16].  The register is used to control the gap between the power down  enter command on the sdram pad to active the dfi_lp_req.
                                                                * This register valid only when the reg_ddrc_dfilp_en = 1'b1.
                                                                * Delay Unit = tCK.
                                                                * Default Vale : 0x8  */
            __IOM uint32_t reg_ddrc_dfilp2pd_gap : 8;                    /* bit[31,24].  The register is used to control the gap between the low dfi_lp_ack to pd-refresh exit command on the sdram pad.
                                                                * This register valid only when the reg_ddrc_dfilp_en = 1'b1.
                                                                * Delay Unit = tCK.
                                                                * Default Vale : 0x8  */
        } reg_0x084_b;
    };

    union {
        __IOM uint32_t reg_0x088;
        struct {
            __IOM uint32_t reg_ddrc_rd_gap_of_diff_rank : 8;                    /* bit[7,0].  When the controller is in mutl-rank configurations, this register is used to control the number of clocks of gap when performing consecutive reads to different banks.
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_ddrc_wr_gap_of_diff_rank : 8;                    /* bit[15,8].  When the controller is in mutl-rank configurations, this register is used to control the number of clocks of gap when performing consecutive writes to different banks.
                                                                * Default Vale : 0xf  */
                uint32_t  : 16;
        } reg_0x088_b;
    };

    union {
        __IOM uint32_t reg_0x08c;
        struct {
            __IOM uint32_t reg_two_rank_auto_ref_diff_r0 : 8;                    /* bit[7,0].  The auto refresh counter start value of rank0 will decrease this value as the start value of the auto refresh counter. It will have the influence to the auto refresh interval of the two rank.
                                                                * The |reg_two_rank_auto_ref_diff_r1 - reg_two_rank_auto_ref_diff_r0| will control the interval of the auto refresh operation between the two ranks.
                                                                * This value shoule be smaller then the reg_ddrc_t_refi_x32.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_two_rank_auto_ref_diff_r1 : 8;                    /* bit[15,8].  The auto refresh counter start value of rank1 will decrease this value as the start value of the auto refresh counter. It will have the influence to the auto refresh interval of the two rank.
                                                                * The |reg_two_rank_auto_ref_diff_r1 - reg_two_rank_auto_ref_diff_r0| will control the interval of the auto refresh operation between the two ranks.
                                                                * This value shoule be smaller then the reg_ddrc_t_refi_x32.
                                                                * Default Vale : 0x1f  */
            __IOM uint32_t reg_two_rank_auto_ref_diff_r2 : 8;                    /* bit[23,16].  The auto refresh counter start value of rank2 will decrease this value as the start value of the auto refresh counter. It will have the influence to the auto refresh interval of the two rank.
                                                                * The |reg_two_rank_auto_ref_diff_r2 - reg_two_rank_auto_ref_diff_r1| will control the interval of the auto refresh operation between the two ranks.
                                                                * This value shoule be smaller then the reg_ddrc_t_refi_x32.
                                                                * Default Vale : 0x1f  */
            __IOM uint32_t reg_two_rank_auto_ref_diff_r3 : 8;                    /* bit[31,24].  The auto refresh counter start value of rank3 will decrease this value as the start value of the auto refresh counter. It will have the influence to the auto refresh interval of the two rank.
                                                                * The |reg_two_rank_auto_ref_diff_r3 - reg_two_rank_auto_ref_diff_r2| will control the interval of the auto refresh operation between the two ranks.
                                                                * This value shoule be smaller then the reg_ddrc_t_refi_x32.
                                                                * Default Vale : 0x10  */
        } reg_0x08c_b;
    };

    union {
        __IOM uint32_t reg_0x090;
        struct {
            __IOM uint32_t reg_ddrc_wr2rd_of_diff_rank : 8;                    /* bit[7,0].  The register is used to control the timing gap of the write to read operation between two ranks.
                                                                * Default Vale : 0x7  */
            __IOM uint32_t reg_ddrc_rd2wr_of_diff_rank : 8;                    /* bit[15,8].  The register is used to control the timing gap of the read to write operation between two ranks.
                                                                * For LPDDR3: reg_ddrc_rd2wr_of_diff_rank >= (RL+4-WL)/2+1
                                                                * Default Vale : 0x7  */
                uint32_t  : 16;
        } reg_0x090_b;
    };

    __IOM uint32_t reg_0x094;                /* This register is used to control the first load mode register and load mode value of rank0 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x098;                /* This register is used to control the second load mode register and load mode value of rank0 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x09c;                /* This register is used to control the third load mode register and load mode value of rank0 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0a0;                /* This register is used to control the fourth load mode register and load mode value of rank0 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0a4;                /* This register is used to control the fifth load mode register and load mode value of rank0 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0a8;                /* This register is used to control the sixth load mode register and load mode value of rank0 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0ac;                /* This register is used to control the seventh load mode register and load mode value of rank0 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0b0;                /* This register is used to control the eight load mode register and load mode value of rank0 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0b4;                /* This register is used to control the first load mode register and load mode value of rank1 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0b8;                /* This register is used to control the second load mode register and load mode value of rank1 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0bc;                /* This register is used to control the third load mode register and load mode value of rank1 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0c0;                /* This register is used to control the fourth load mode register and load mode value of rank1 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0c4;                /* This register is used to control the fifth load mode register and load mode value of rank1 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0c8;                /* This register is used to control the sixth load mode register and load mode value of rank1 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0cc;                /* This register is used to control the seventh load mode register and load mode value of rank1 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0d0;                /* This register is used to control the eight load mode register and load mode value of rank1 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0d4;                /* This register is used to control the first load mode register and load mode value of rank2 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0d8;                /* This register is used to control the second load mode register and load mode value of rank2 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0dc;                /* This register is used to control the third load mode register and load mode value of rank2 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0e0;                /* This register is used to control the fourth load mode register and load mode value of rank2 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0e4;                /* This register is used to control the fifth load mode register and load mode value of rank2 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0e8;                /* This register is used to control the sixth load mode register and load mode value of rank2 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0ec;                /* This register is used to control the seventh load mode register and load mode value of rank2 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0f0;                /* This register is used to control the eight load mode register and load mode value of rank2 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0f4;                /* This register is used to control the first load mode register and load mode value of rank3 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0f8;                /* This register is used to control the second load mode register and load mode value of rank3 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x0fc;                /* This register is used to control the third load mode register and load mode value of rank3 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x100;                /* This register is used to control the fourth load mode register and load mode value of rank3 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x104;                /* This register is used to control the fifth load mode register and load mode value of rank3 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x108;                /* This register is used to control the sixth load mode register and load mode value of rank3 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x10c;                /* This register is used to control the seventh load mode register and load mode value of rank3 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x110;                /* This register is used to control the eight load mode register and load mode value of rank3 when enable the user load mode function.
                                                                * The bit[25] is used to means the valid of this load mode value.
                                                                * For DDR3 mode, the bit[15:14] is used to control the load mode address and  bit[13:0] is used to control the load mode value.
                                                                * For DDR4 mode, the bit[20:18] is used to control the load mode address and bit[17:0] is used to control the load mode value.
                                                                * Note:The minimum gap between the two load mode command of same rank is 6*Tck when enable the user load mode function. So the register reg_ddrc_tmrd can be valid only when reg_ddrc_tmrd > 6Tck.
                                                                * Default Vale : 0x0  */

    union {
        __IOM uint32_t reg_0x114;
        struct {
            __IOM uint32_t reg_init_lpddr4_mrw_2_en : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_init_lpddr4_mrw_1_en : 1;                    /* bit[1].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_init_lpddr4_mrr_en : 1;                    /* bit[2].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_init_lpddr4_mrr0_mrw1 : 1;                    /* bit[3].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_user_load_mode_en : 1;                    /* bit[4].  When this bit change from low to high, the controller will trigger the user load mode function and generate the load mode command. The load mode address and value is controlled using the register reg_user_load_mode_value(reg0x24[23:0]).
                                                                * Default Vale : 0x0  */
                uint32_t  : 27;
        } reg_0x114_b;
    };

    union {
        __IOM uint32_t reg_0x118;
        struct {
            __IOM uint32_t reg_ddrc_ecc_poison_bank : 4;                    /* bit[3,0].  The bank number of the read address which chooses for the ECC poison.
                                                                * When the IMC chooses DDR3 mode, the bank[2:0] means the bank number.
                                                                * When the IMC chooses DDR4 mode, the bank[1:0] means the bank number, the bank[3:2] means the bank group number.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_ecc_poison_rank : 1;                    /* bit[4].  The rank number of the read address which chooses for the ECC poison.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_ecc_poison_sdram_beat : 2;                    /* bit[6,5].  Select the dfi write beat which need to be posion.
                                                                * For the 1:2 mode and burst8, the dfi write beats is 2 for each write command.
                                                                * For the 1:2 mode and burst16, the dfi write beats is 4 for each write command.
                                                                * Default Vale : 0x0  */
                uint32_t  : 7;
            __IOM uint32_t reg_ddrc_ecc_poison_en : 1;                    /* bit[14].  The Enable signal of the data poison mode when enable the Sideband ECC function or Inline ECC Function. Active High. When enable the data poison mode, the controller will monitor the read back data. If  the read back data which belongs to the reg_ddrc_ecc_posion_rank/bank/row/col, it will inject the error to the read back data. The error bit is controllered by the reg_ddrc_ecc_poison_sdram_beat and reg_ddrc_ecc_poison_bit_num.
                                                                * 0: Disable the data poison mode.
                                                                * 1: Enable the data poison mode.
                                                                * Default Vale : 0x0  */
                uint32_t  : 1;
            __IOM uint32_t reg_ddrc_ecc_corr_err_info_clr : 1;                    /* bit[16].  When this register set to 1, it will clean the reg_ddrc_ecc_corr_err_rank, reg_ddrc_ecc_corr_err_bank,reg_ddrc_ecc_corr_err_row, reg_ddrc_ecc_corr_exp_data, reg_ddrc_ecc_corr_act_data and reg_ddrc_ecc_corr_err_col.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_ecc_uncorr_err_info_clr : 1;                    /* bit[17].  When this register set to 1, it will clean the reg_ddrc_ecc_uncorr_err_rank, reg_ddrc_ecc_uncorr_err_bank,reg_ddrc_ecc_uncorr_err_row, reg_ddrc_ecc_uncorr_exp_data, reg_ddrc_ecc_uncorr_act_data and reg_ddrc_ecc_uncorr_err_col.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_ecc_corr_err_cnt_clr : 1;                    /* bit[18].  When this register set to 1, it will clear the reg_ddrc_ecc_corr_err_cnt, reg_ddrc_ecc_corr_bit_num, rand reg_ddrc_ecc_corr_err.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_ecc_uncorr_err_cnt_clr : 1;                    /* bit[19].  When this register set to 1, it will clear the reg_ddrc_ecc_uncorr_err_cnt, reg_ddrc_ecc_uncorr_bit_num and reg_ddrc_ecc_uncorr_err.
                                                                * Default Vale : 0x0  */
                uint32_t  : 4;
            __IOM uint32_t reg_ddrc_ecc_dis_scrub : 1;                    /* bit[24].  The disable signal of the scrub funtion when the reg_ddrc_ecc_en set to 1'b1. Active High.
                                                                * 1: When the IMC detected the corrected error, it will only send the corrected data to the master.
                                                                * 0: When the IMC detected the corrected error, it will not only send the corrected data to the master but also use the RMW to correct the data in the SDRAM.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_ddrc_ecc_en : 1;                    /* bit[25].  The enable signal of the ECC function. Active High.
                                                                * 1: Enable the ECC function.
                                                                * 0: Disable the ECC function.
                                                                * Default Vale : 0x0  */
                uint32_t  : 6;
        } reg_0x118_b;
    };

    union {
        __IOM uint32_t reg_0x11c;
        struct {
            __IOM uint32_t reg_ddrc_ecc_poison_col : 12;                    /* bit[11,0].  The col number of the read address which chooses for the ECC poison.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_ecc_poison_row : 17;                    /* bit[28,12].  The row number of the read address which chooses for the ECC poison.
                                                                * Default Vale : 0x0  */
                uint32_t  : 3;
        } reg_0x11c_b;
    };

    __IOM uint32_t reg_0x120;                /* The start address of the protect system address for inline ecc function. When the one ddr burst data is larger than the axi data width, the start address should align to the ddr burst data.
                                                                * If the axi access transfer belong to the [reg_inine_ecc_protect_end_addr:reg_inline_ecc_protect_start_addr], that transfer will marked to a protected transfer and will generate the inline ecc command.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x124;                /* The end address of the protect system address for inline ecc function. When the one ddr burst data is larger than the axi data width, the start address should align to the ddr burst data.
                                                                * If the axi access transfer belong to the [reg_inine_ecc_protect_end_addr:reg_inline_ecc_protect_start_addr], that transfer will marked to a protected transfer and will generate the inline ecc command.
                                                                * Default Vale : 0x0  */

    union {
        __IOM uint32_t reg_0x128;
        struct {
            __IOM uint32_t reg_ddrc_efficiency_cal_en : 1;                    /* bit[0].  Related to ddr effiiciency calculated,enabled the caculated.                                                                                    1: start to caculate ddr effiiciency.                                                                                                                                   0: don't start to caculate ddr effiiciency.  
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_cal_efficiency_number_cnt : 3;                    /* bit[3,1].  Related to ddr effiiciency calculated,the caculated times.
                                                                * Default Vale : 0x0  */
                uint32_t  : 28;
        } reg_0x128_b;
    };

    __IOM uint32_t reg_0x12c;                /* Related to ddr effiiciency calculated,how many core_clk cycle are counted at a time.
                                                                * Default Vale : 0x7fffffff  */

    union {
        __IOM uint32_t reg_0x130;
        struct {
            __IOM uint32_t reg_rd_port_urgent_en0 : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rd_port_aging_en0 : 1;                    /* bit[1].  The enable signal of aging function for the read operation of axi slave port0. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_rd_port_priority0 : 10;                    /* bit[13,4].  The initial load value of read aging counters for axi slave port0. The value will be load after the system reset or after write operation grant to the axi slave port 0. The aging coutners decreas every clock cycle when the port 0 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_urgent_en0 : 1;                    /* bit[16].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_wr_port_aging_en0 : 1;                    /* bit[17].  The enable signal of aging function for the write opdration of axi slave port0. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_priority0 : 10;                    /* bit[29,20].  The initial load value of write aging counters for axi slave port0. The value will be load after the system reset or after write operation grant to the axi slave port 0. The aging coutners decreas every clock cycle when the port 0 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
        } reg_0x130_b;
    };

    union {
        __IOM uint32_t reg_0x134;
        struct {
            __IOM uint32_t reg_rd_port_urgent_en1 : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rd_port_aging_en1 : 1;                    /* bit[1].  The enable signal of aging function for the read operation of axi slave port1. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_rd_port_priority1 : 10;                    /* bit[13,4].  The initial load value of read aging counters for axi slave port1. The value will be load after the system reset or after write operation grant to the axi slave port 1. The aging coutners decreas every clock cycle when the port 1 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_urgent_en1 : 1;                    /* bit[16].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_wr_port_aging_en1 : 1;                    /* bit[17].  The enable signal of aging function for the write opdration of axi slave port1. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_priority1 : 10;                    /* bit[29,20].  The initial load value of write aging counters for axi slave port1. The value will be load after the system reset or after write operation grant to the axi slave port 1. The aging coutners decreas every clock cycle when the port 1 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
        } reg_0x134_b;
    };

    union {
        __IOM uint32_t reg_0x138;
        struct {
            __IOM uint32_t reg_rd_port_urgent_en2 : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rd_port_aging_en2 : 1;                    /* bit[1].  The enable signal of aging function for the read operation of axi slave port2. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_rd_port_priority2 : 10;                    /* bit[13,4].  The initial load value of read aging counters for axi slave port2. The value will be load after the system reset or after write operation grant to the axi slave port 2. The aging coutners decreas every clock cycle when the port 2 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_urgent_en2 : 1;                    /* bit[16].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_wr_port_aging_en2 : 1;                    /* bit[17].  The enable signal of aging function for the write opdration of axi slave port2. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_priority2 : 10;                    /* bit[29,20].  The initial load value of write aging counters for axi slave port2. The value will be load after the system reset or after write operation grant to the axi slave port 2. The aging coutners decreas every clock cycle when the port 2 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
        } reg_0x138_b;
    };

    union {
        __IOM uint32_t reg_0x13c;
        struct {
            __IOM uint32_t reg_rd_port_urgent_en3 : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rd_port_aging_en3 : 1;                    /* bit[1].  The enable signal of aging function for the read operation of axi slave port3. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_rd_port_priority3 : 10;                    /* bit[13,4].  The initial load value of read aging counters for axi slave port3. The value will be load after the system reset or after write operation grant to the axi slave port 3. The aging coutners decreas every clock cycle when the port 3 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_urgent_en3 : 1;                    /* bit[16].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_wr_port_aging_en3 : 1;                    /* bit[17].  The enable signal of aging function for the write opdration of axi slave port3. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_priority3 : 10;                    /* bit[29,20].  The initial load value of write aging counters for axi slave port3. The value will be load after the system reset or after write operation grant to the axi slave port 3. The aging coutners decreas every clock cycle when the port 3 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
        } reg_0x13c_b;
    };

    union {
        __IOM uint32_t reg_0x140;
        struct {
            __IOM uint32_t reg_rd_port_urgent_en4 : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rd_port_aging_en4 : 1;                    /* bit[1].  The enable signal of aging function for the read operation of axi slave port4. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_rd_port_priority4 : 10;                    /* bit[13,4].  The initial load value of read aging counters for axi slave port4. The value will be load after the system reset or after write operation grant to the axi slave port 4. The aging coutners decreas every clock cycle when the port 4 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_urgent_en4 : 1;                    /* bit[16].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_wr_port_aging_en4 : 1;                    /* bit[17].  The enable signal of aging function for the write opdration of axi slave port4. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_priority4 : 10;                    /* bit[29,20].  The initial load value of write aging counters for axi slave port4. The value will be load after the system reset or after write operation grant to the axi slave port 4. The aging coutners decreas every clock cycle when the port 4 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
        } reg_0x140_b;
    };

    union {
        __IOM uint32_t reg_0x144;
        struct {
            __IOM uint32_t reg_rd_port_urgent_en5 : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rd_port_aging_en5 : 1;                    /* bit[1].  The enable signal of aging function for the read operation of axi slave port5. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_rd_port_priority5 : 10;                    /* bit[13,4].  The initial load value of read aging counters for axi slave port5. The value will be load after the system reset or after write operation grant to the axi slave port 5. The aging coutners decreas every clock cycle when the port 5 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_urgent_en5 : 1;                    /* bit[16].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_wr_port_aging_en5 : 1;                    /* bit[17].  The enable signal of aging function for the write opdration of axi slave port5. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_priority5 : 10;                    /* bit[29,20].  The initial load value of write aging counters for axi slave port5. The value will be load after the system reset or after write operation grant to the axi slave port 5. The aging coutners decreas every clock cycle when the port 5 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
        } reg_0x144_b;
    };

    union {
        __IOM uint32_t reg_0x148;
        struct {
            __IOM uint32_t reg_rd_port_urgent_en6 : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rd_port_aging_en6 : 1;                    /* bit[1].  The enable signal of aging function for the read operation of axi slave port6. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_rd_port_priority6 : 10;                    /* bit[13,4].  The initial load value of read aging counters for axi slave port6. The value will be load after the system reset or after write operation grant to the axi slave port 6. The aging coutners decreas every clock cycle when the port 6 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_urgent_en6 : 1;                    /* bit[16].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_wr_port_aging_en6 : 1;                    /* bit[17].  The enable signal of aging function for the write opdration of axi slave port6. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_priority6 : 10;                    /* bit[29,20].  The initial load value of write aging counters for axi slave port6. The value will be load after the system reset or after write operation grant to the axi slave port 6. The aging coutners decreas every clock cycle when the port 6 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
        } reg_0x148_b;
    };

    union {
        __IOM uint32_t reg_0x14c;
        struct {
            __IOM uint32_t reg_rd_port_urgent_en7 : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rd_port_aging_en7 : 1;                    /* bit[1].  The enable signal of aging function for the read operation of axi slave port7. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_rd_port_priority7 : 10;                    /* bit[13,4].  The initial load value of read aging counters for axi slave port7. The value will be load after the system reset or after write operation grant to the axi slave port 7. The aging coutners decreas every clock cycle when the port 7 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_urgent_en7 : 1;                    /* bit[16].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_wr_port_aging_en7 : 1;                    /* bit[17].  The enable signal of aging function for the write opdration of axi slave port7. Active high.
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_wr_port_priority7 : 10;                    /* bit[29,20].  The initial load value of write aging counters for axi slave port7. The value will be load after the system reset or after write operation grant to the axi slave port 7. The aging coutners decreas every clock cycle when the port 7 has write request but not granted. The port's priority increases when the aging counter starts to decrease. When the aging counter becomes 0, the corresponding port has the highest priority level. For signle port, the aging counters are only used when the timout change to 0 to force read-write direction switching.
                                                                * Default Vale : 0x123  */
                uint32_t  : 2;
        } reg_0x14c_b;
    };

    union {
        __IOM uint32_t reg_0x150;
        struct {
            __IOM uint32_t reg_prefer_write : 1;                    /* bit[0].  If the register set to high, when the write and read request has the same priority, the write has high priroty.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_pagematch_limit : 1;                    /* bit[1].  Reserved.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_go2critical_en : 1;                    /* bit[2].  Reserved.
                                                                * Default Vale : 0x0  */
                uint32_t  : 13;
            __IOM uint32_t reg_wr_starve_time : 16;                    /* bit[31,16].  Used to control the number of core clocks that the write request changes to the starve which will have highest priority. The minimum valid value is 0x1. When the value set to 0x0, it will disable the starvation functions.
                                                                * Default Vale : 0x1f  */
        } reg_0x150_b;
    };

    union {
        __IOM uint32_t reg_0x154;
        struct {
            __IOM uint32_t reg_wr2rd_switch_threhold : 8;                    /* bit[7,0].  Indicates the max transaction that the read operation can be dealed with after the grant to the read request from the starvation functions.
                                                                * Default Vale : 0x5  */
            __IOM uint32_t reg_rd2wr_switch_threhold : 8;                    /* bit[15,8].  Indicates the max transaction that the write operation can be dealed with after the grant to the write request from the starvation functions.
                                                                * Default Vale : 0x1a  */
            __IOM uint32_t reg_rd_starve_time : 16;                    /* bit[31,16].  Used to control the number of core clocks that the read request changes to the starve which will have highest priority. The minimum valid value is 0x1. When the value set to 0x0, it will disable the starvation functions.
                                                                * Default Vale : 0x1f  */
        } reg_0x154_b;
    };

    union {
        __IOM uint32_t reg_0x158;
        struct {
            __IOM uint32_t reg_rcmd_pend_to_starve_max_time : 13;                    /* bit[19,7].  The register used to control the initial value of the read command pending state in the read command queue.
                                                                * When the read command is stored in the command queue, the read command will have a pending initial value and load to the counter. The counter will be decreased until this read command is scheduled. When this counter is decreaed to 8'h0, this pending read command will be in the starve state and has the highest priority.
                                                                * Default Vale : 0x1fff  */
            __IOM uint32_t reg_rcmd_pend_to_starve_flag_en : 1;                    /* bit[20].  The enable signal of the read command starve function in the read command queue. Active High.
                                                                * 1: The read command which is pending in the read command queue will be go into the starve state when the starve conter is decreased to 8'h0.
                                                                * 0: Disable the starve function of the read commands which are in the command queue.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_vpr_time_out_init_value : 11;                    /* bit[31,21].  nan
                                                                * Default Vale : 0x7ff  */
        } reg_0x158_b;
    };

    union {
        __IOM uint32_t reg_0x15c;
        struct {
            __IOM uint32_t reg_wqos_level1 : 4;                    /* bit[3,0].  Used to control the priority of the write command.
                                                                * When the axi_wqos <= reg_wqos_level1, the axi write transfer is Low Priority Write Command.
                                                                * When the axi_wqos > reg_wqos_level1 & axi_wqos <= reg_wqos_level2, the axi wire transfer is Variable Priority Write Command.
                                                                * Default Vale : 0x3  */
            __IOM uint32_t reg_wqos_level2 : 4;                    /* bit[7,4].  Reserved.
                                                                * Default Vale : 0x7  */
            __IOM uint32_t reg_wqos_value_region0 : 2;                    /* bit[9,8].  The qos value of the Low Priority Read Command.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_wqos_value_region1 : 2;                    /* bit[11,10].  The qos value of the Variable Priority Write Command.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_wqos_value_region2 : 2;                    /* bit[13,12].  Reserved.
                                                                * Default Vale : 0x2  */
                uint32_t  : 2;
            __IOM uint32_t reg_rqos_level1 : 4;                    /* bit[19,16].  Used to control the priority of the read command.
                                                                * When the axi_rqos <= reg_rqos_level1, the axi read transfer is Low Priority Read Command.
                                                                * When the axi_rqos > reg_rqos_level1 & axi_rqos <= reg_rqos_level2, the axi read transfer is Variable Priority Read Command.
                                                                * When the axi_rqos > reg_rqos_level12, the axi read transfer is High Priority Read Command.
                                                                * Default Vale : 0x3  */
            __IOM uint32_t reg_rqos_level2 : 4;                    /* bit[23,20].  Used to control the priority of the read command.
                                                                * When the axi_rqos <= reg_rqos_level1, the axi read transfer is Low Priority Read Command.
                                                                * When the axi_rqos > reg_rqos_level1 & axi_rqos <= reg_rqos_level2, the axi read transfer is Variable Priority Read Command.
                                                                * When the axi_rqos > reg_rqos_level12, the axi read transfer is High Priority Read Command.
                                                                * Default Vale : 0x6  */
            __IOM uint32_t reg_rqos_value_region0 : 2;                    /* bit[25,24].  The qos value of the Low Priority Read Command.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rqos_value_region1 : 2;                    /* bit[27,26].  The qos value of the Variable Priority Read Command.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_rqos_value_region2 : 2;                    /* bit[29,28].  The qos value of the High Priority Read Command.
                                                                * Default Vale : 0x2  */
                uint32_t  : 2;
        } reg_0x15c_b;
    };

    union {
        __IOM uint32_t reg_0x160;
        struct {
            __IOM uint32_t reg_ddrc_wodt_st_bp : 1;                    /* bit[0].  The bypass enable signal to control the delay between the write command to the dfi odt.
                                                                * 1: Choose to use the reg_ddrc_wodt_delay to control.
                                                                * 0: According to use the CWL to control the delay automatically.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_wodt_always_open : 1;                    /* bit[1].  The enable signal to set the dfi_odt  to 4'hf and keep unchaged. Active High.
                                                                * 1: The dfi_odt will always output 4'hf to make the ODT keep high.
                                                                * 0: The dfi_odt is controllered by other signals.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_wodt_disable : 1;                    /* bit[2].  The wodt enable signal. Active Low.
                                                                * 0: The dfi_odt will generate based on the reg_ddrc_wodt_length and reg_ddrc_wodt_delay at the write operation.
                                                                * 1: The dfi_odt will output the 4'h0 and keep unchanged. The reg_ddrc_wodt_always_open will have higer priority.
                                                                * Default Vale : 0x0  */
                uint32_t  : 5;
            __IOM uint32_t reg_ddrc_wodt_length : 5;                    /* bit[12,8].  The register used to control the legnth of the write odt. Length unit: tCK. The min support value is 2.
                                                                * Eg. When this register set to 4'h6, the the write odt will keep 6 tCK. This value only can be set to the even number.
                                                                * Default Vale : 0x6  */
                uint32_t  : 3;
            __IOM uint32_t reg_ddrc_wodt_delay : 6;                    /* bit[21,16].  The register used to control the delay between the write command and odt.  So it will decide the start point of the ODT. The delay unit is tCK. The min supoort value is 2.
                                                                * Default Vale : 0x2  */
                uint32_t  : 10;
        } reg_0x160_b;
    };

    union {
        __IOM uint32_t reg_0x164;
        struct {
            __IOM uint32_t reg_cwl_al_cl_bp : 1;                    /* bit[0].  The CWL/AL/CL parameter configure byass enable signal. Active.
                                                                * 1: Using the reg_al_bp/reg_cwl_bp/reg_cl_bp to control the value of the CWL/ACL/CL in the controller which will control the dfi interface timing.
                                                                * 0: The controller will automatically update the CWL/AL/CL value from the load mode operation. 
                                                                * Default Vale : 0x0  */
                uint32_t  : 7;
            __IOM uint32_t reg_cl_bp : 6;                    /* bit[13,8].  The bypass cl value when the reg_cwl_al_cl_bp = 1'b1.
                                                                * Default Vale : 0x7  */
                uint32_t  : 2;
            __IOM uint32_t reg_cwl_bp : 6;                    /* bit[21,16].  The bypass cwl value when the reg_cwl_al_cl_bp = 1'b1.
                                                                * Default Vale : 0x8  */
                uint32_t  : 2;
            __IOM uint32_t reg_al_bp : 5;                    /* bit[28,24].  The bypass al value when the reg_cwl_al_cl_bp = 1'b1.
                                                                * Default Vale : 0x0  */
                uint32_t  : 3;
        } reg_0x164_b;
    };

    union {
        __IOM uint32_t reg_0x168;
        struct {
            __IOM uint32_t reg_dfi_trdata_en_bp : 1;                    /* bit[0].  Enable the bypass mode to control the timing parameters tPHY_RDDATA_EN which means the delay between the dfi read command to dfi_rddata_en. Active High.
                                                                * 0: The controller will use the AL/CL/RL to control the timing parameters tPHY_RDDATA_EN.
                                                                * 1: The controller will use the reg_dfi_tphy_wrlat to control the delay between the dfi read command to dfi_rddata_en.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_dfi_tphy_wrlat_bp : 1;                    /* bit[1].  Enable the bypass mode to control the timing parameters tPHY_WRLAT which means the delay between the dfi write command to dfi_wrdata/dfi_wrdata_en. Active High.
                                                                * 0: The controller will use the CWL/AL/WL to control the timing parameters tPHY_WRLAT.
                                                                * 1: The controller will use the register reg_dfi_tphy_wrlat to control the timing parameters tPHY_WRLAT.
                                                                * Default Vale : 0x0  */
                uint32_t  : 6;
            __IOM uint32_t reg_dfi_trdata_en : 5;                    /* bit[12,8].  The register is used to control the delaythe timing parameters tPHY_RDDATA_EN when the reg_dfi_trdata_en_bp set to 1'b1.
                                                                * Default Vale : 0x0  */
                uint32_t  : 3;
            __IOM uint32_t reg_ddrc_tctrl_delay : 8;                    /* bit[23,16].   
                                                                * It is the delay of the command from the dfi interface to command pad of the PHY that the controller will connect. It is the timing parameters of the PHY that the controller should know.
                                                                * The users need to check the timing parameters(tctrl_delay) of the PHY and configure the same value to this register.
                                                                * Default Vale : 0x6  */
            __IOM uint32_t reg_dfi_tphy_wrlat : 5;                    /* bit[28,24].  The register is used to control the timing parameters tPHY_WRLAT  when the reg_dfi_tphy_wralt_bp set to 1'b1.
                                                                * Default Vale : 0x0  */
                uint32_t  : 3;
        } reg_0x168_b;
    };

    union {
        __IOM uint32_t reg_0x16c;
        struct {
            __IOM uint32_t reg_wqueue_max_dep : 7;                    /* bit[6,0].  This register is used to control the write command queue depth which used for write command reorder. The max depth is 64.
                                                                * Default Vale : 0x40  */
                uint32_t  : 1;
            __IOM uint32_t reg_lp_rqueue_max_dep : 7;                    /* bit[14,8].  This register is used to control the read command queue depth which used for read command reorder. The max depth is 64. When enable the Sideband ECC or Inline ECC function, this register should set to 'd63 becuase of the last cell used for the scrub command. When disable the ECC function, this register should set to 'd64. 
                                                                * Default Vale : 0x40  */
                uint32_t  : 1;
            __IOM uint32_t reg_hp_rqueue_max_dep : 7;                    /* bit[22,16].  Reserved.
                                                                * Default Vale : 0x0  */
                uint32_t  : 1;
            __IOM uint32_t reg_wqueue_ecc_max_dep : 6;                    /* bit[29,24].  This register is used to control the write ecc command queue depth which used for write ecc command reorder when enable the inline ecc function. The max depth is 32.
                                                                * Default Vale : 0x20  */
                uint32_t  : 2;
        } reg_0x16c_b;
    };

    union {
        __IOM uint32_t reg_0x170;
        struct {
            __IOM uint32_t reg_bist_en : 1;                    /* bit[0].  The enable signal of the bist module. High valid.
                                                                * 1: Enable.
                                                                * 0: Disable.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_bist_start : 1;                    /* bit[1].  The start signals the bist function. This signal is valid only when the bist module is enable( reg0x1a4[0] = 1 ).
                                                                * 0: Disable State.
                                                                * 1: Start the bist function.
                                                                * Note: The bist start signal is positive edge enable. Before the next time you want to start the bist function, you need to low this bit firstly.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_bist_soft_rstn : 1;                    /* bit[2].  The soft reset signal of the bist module.
                                                                * 0: Disable State.
                                                                * 1: Start the bist function.
                                                                * Note: The bist start signal is positive edge enable. Before the next time you want to start the bist function, you need to low this bit firstly.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_bist_serial_wr_stop : 1;                    /* bit[3].  The disable signal of successive write read bist mode for bist function.
                                                                * 0: Keep.
                                                                * 1: Stop the successive write read bist mode.
                                                                * Note: When the bist module is in the successive write read mode, If it detects this signal is high, it will stop to do the write and read operation when they complete the current write and read operation.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_bist_mode_sel : 3;                    /* bit[6,4].  Choose the bist function mode.
                                                                * Default Vale : 0x3  */
            __IOM uint32_t reg_bist_data_pattern_sel : 3;                    /* bit[9,7].  Choose the bist data generate pattern.
                                                                * 000:Fix data.
                                                                * 001:Register Config Data. Related register: 0x1b0.
                                                                * 010:ALL DQs are the different Random Data.
                                                                * 011:ALL DQs are the same Random Data.
                                                                * Default Vale : 0x2  */
            __IOM uint32_t reg_bist_addr_pattern_sel : 3;                    /* bit[12,10].  Choose the bist address generate pattern.
                                                                * 000:x-fast and forward mode.
                                                                * 001:y-fast and forward mode.
                                                                * 010:x-fast and backward mode.
                                                                * 011:y-fast and backward mode.
                                                                * 100:z-fast and forward mode.
                                                                * 101:z-fast and backward mode.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_bist_data_obs_sel : 1;                    /* bit[13].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_bit_sel : 4;                    /* bit[17,14].  Used to control the bist data pattern when reg_bist_data_pattern_sel = 3'b011.
                                                                * When the regi_bist_data_pattern_sel = 3'b011, the all DQs will generate the same random data.  
                                                                * There are 16 patterns that you can choose.
                                                                * Default Vale : 0x0  */
                uint32_t  : 14;
        } reg_0x170_b;
    };

    __IOM uint32_t reg_0x174;                /* DQ data mask
                                                                * Default Vale : 0xffffffff  */

    __IOM uint32_t reg_0x178;                /* Choose the start address of the MEM-BIST.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x17c;                /* Choose the end address of the MEM-BIST.
                                                                * Default Vale : 0x40000000  */

    __IOM uint32_t reg_0x180;                /* Configure the bist pattern of the MEM-BIST when reg_bist_data_pattern_sel = 2'b01.
                                                                * Default Vale : 0x2143005a  */

    __IOM uint32_t reg_0x184;                /* Configure the bist pattern of the MEM-BIST when reg_bist_data_pattern_sel = 2'b01.
                                                                * Default Vale : 0X0  */

    __IOM uint32_t reg_0x188;                /* Configure the bist pattern of the MEM-BIST when reg_bist_data_pattern_sel = 2'b01.
                                                                * Default Vale : 0X0  */

    __IOM uint32_t reg_0x18c;                /* Configure the bist pattern of the MEM-BIST when reg_bist_data_pattern_sel = 2'b01.
                                                                * Default Vale : 0X0  */

    __IOM uint32_t reg_0x190;                /* Configure the bist pattern of the MEM-BIST when reg_bist_data_pattern_sel = 2'b01.
                                                                * Default Vale : 0X0  */

    __IOM uint32_t reg_0x194;                /* This signal is used to choose random sequence type prbs15 or prbs11 when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x1  */

    __IOM uint32_t reg_0x198;                /* DQ:0-31 data mask
                                                                * Default Vale : 0xffffffff  */

    __IOM uint32_t reg_0x19c;                /* DQ :32-63 data mask
                                                                * Default Vale : 0xffffffff  */

    __IOM uint32_t reg_0x1a0;                /* DQ :64-79 data mask
                                                                * Default Vale : 0xffff  */

    __IOM uint32_t reg_0x1a4;                /* error data count set for error data test
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x1a8;                /* error address set for error data test, reg_bist_eaddr_set[7:0] valid, error set for bist_address when 
                                                                * bist_address[7:0] == reg_bist_eaddr_set[7:0].
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x1ac;                /* error DQ set for error data test. when dq16, reg_bist_ebit_set_0[15:0] valid, reg_bist_ebit_set_1 and reg_bist_ebit_set_2 unvalid. set 0 for bit which you want to set error.
                                                                * Default Vale : 0xffffffff  */

    __IOM uint32_t reg_0x1b0;                /* error DQ set for error data test. when dq16, reg_bist_ebit_set_0[15:0] valid, reg_bist_ebit_set_1 and reg_bist_ebit_set_2 unvalid. set 0 for bit which you want to set error.
                                                                * Default Vale : 0xffffffff  */

    __IOM uint32_t reg_0x1b4;                /* error DQ set for error data test. when dq16, reg_bist_ebit_set_0[15:0] valid, reg_bist_ebit_set_1 and reg_bist_ebit_set_2 unvalid. set 0 for bit which you want to set error.
                                                                * Default Vale : 0xffffffff  */

    __IOM uint32_t reg_0x1b8;                /* Choose which DQ error count to output. For dq16, 0-15 can be set.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x1bc;                /* DQ error count
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x1c0;                /* DQ0/1 random seed  when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x45ba_6492  */

    __IOM uint32_t reg_0x1c4;                /* DQ2/3 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x55aa_ab69  */

    __IOM uint32_t reg_0x1c8;                /* DQ4/5 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x6699_fa39  */

    __IOM uint32_t reg_0x1cc;                /* DQ6/7 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x5aa5_95de  */

    __IOM uint32_t reg_0x1d0;                /* DQ8/9 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0xd2cc_462c  */

    __IOM uint32_t reg_0x1d4;                /* DQ10/DQ11 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x67ee_ba83  */

    __IOM uint32_t reg_0x1d8;                /* DQ12/DQ13 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x1234_ab58  */

    __IOM uint32_t reg_0x1dc;                /* DQ14/DQ15 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x5678_eda3  */

    __IOM uint32_t reg_0x1e0;                /* DQ16/DQ17 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x5a10_371a  */

    __IOM uint32_t reg_0x1e4;                /* DQ18/DQ19 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x5cda_be69  */

    __IOM uint32_t reg_0x1e8;                /* DQ20/DQ21 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x91de_320d  */

    __IOM uint32_t reg_0x1ec;                /* DQ22/DQ23 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0xbaa6_a091  */

    __IOM uint32_t reg_0x1f0;                /* DQ24/DQ25 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0xcccc_be20  */

    __IOM uint32_t reg_0x1f4;                /* DQ26/DQ27 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0xeeee_bde2  */

    __IOM uint32_t reg_0x1f8;                /* DQ28/DQ29 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x1012_9287  */

    __IOM uint32_t reg_0x1fc;                /* DQ30/DQ31 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x1456_6ad9  */

    __IOM uint32_t reg_0x200;                /* DQ32/DQ33 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x45ba_6492  */

    __IOM uint32_t reg_0x204;                /* DQ34/DQ35 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x55aa_ab69  */

    __IOM uint32_t reg_0x208;                /* DQ36/DQ37 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x6699_fa39  */

    __IOM uint32_t reg_0x20c;                /* DQ38/DQ39 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x5aa5_95de  */

    __IOM uint32_t reg_0x210;                /* DQ40/DQ41 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0xd2cc_462c  */

    __IOM uint32_t reg_0x214;                /* DQ42/DQ43 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x67ee_ba83  */

    __IOM uint32_t reg_0x218;                /* DQ44/DQ45 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x1234_ab58  */

    __IOM uint32_t reg_0x21c;                /* DQ46/DQ47 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x5678_eda3  */

    __IOM uint32_t reg_0x220;                /* DQ48/DQ49 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x5a10_371a  */

    __IOM uint32_t reg_0x224;                /* DQ50/DQ51 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x5cda_be69  */

    __IOM uint32_t reg_0x228;                /* DQ52/DQ53 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x91de_320d  */

    __IOM uint32_t reg_0x22c;                /* DQ54/DQ55 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0xbaa6_a091  */

    __IOM uint32_t reg_0x230;                /* DQ56/DQ57 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0xcccc_be20  */

    __IOM uint32_t reg_0x234;                /* DQ58/DQ59 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0xeeee_bde2  */

    __IOM uint32_t reg_0x238;                /* DQ60/DQ61 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x1012_9287  */

    __IOM uint32_t reg_0x23c;                /* DQ62/DQ63 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x1456_6ad9  */

    __IOM uint32_t reg_0x240;                /* DQ64/DQ65 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x45ba_6492  */

    __IOM uint32_t reg_0x244;                /* DQ66/DQ67 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x55aa_ab69  */

    __IOM uint32_t reg_0x248;                /* DQ68/DQ69 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x6699_fa39  */

    __IOM uint32_t reg_0x24c;                /* DQ70/DQ71 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x5aa5_95de  */

    __IOM uint32_t reg_0x250;                /* DQ72/DQ73 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0xd2cc_462c  */

    __IOM uint32_t reg_0x254;                /* DQ74/DQ75 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x67ee_ba83  */

    __IOM uint32_t reg_0x258;                /* DQ76/DQ77 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x1234_ab58  */

    __IOM uint32_t reg_0x25c;                /* DQ78/DQ79 random seed   when reg_bist_data_pattern_sel = 2'b10.
                                                                * Default Vale : 0x5678_eda3  */

    union {
        __IOM uint32_t reg_0x260;
        struct {
            __IOM uint32_t reg_sdram_col_size : 4;                    /* bit[3,0].  Choose the size of the column.
                                                                * 4'ha: Choose the col bits width is 10.
                                                                * 4'h9: Choose the col bits width is 9.
                                                                * The user needs to accord the sdram capacity to choose the col size.
                                                                * Default Vale : 0xa  */
            __IOM uint32_t reg_sdram_row_size : 5;                    /* bit[8,4].  Choose the size of the row.
                                                                * 4'hf: Choose the row bits width is 15.
                                                                * 4'he: Choose the row bits widths is 14.
                                                                * The user needs to accord the sdram capacity to choose the row size.
                                                                * Default Vale : 0xf  */
            __IOM uint32_t reg_sdram_bank_size : 3;                    /* bit[11,9].  Choose the size of the bank.
                                                                * 3'h3: Support 8 banks.
                                                                * 3'h4: Support 16 banks.
                                                                * The user needs to accord the sdram capacity to choose the bank size.
                                                                * For DDR4, if the ba is 2 bits and bg is 1 bit. The value should set to 3 and the reg_ddrc_bank_offset_bit2 map to bg[0].
                                                                * For DDR4, if the ba is 2 bits and bg is 2 bits. The value should set to 4. The reg_ddrc_bank_offset_bit2 map to bg[0] and the reg_ddrc_bank_offset_bit3_map to bg[1].
                                                                * Default Vale : 0x4  */
                uint32_t  : 2;
            __IOM uint32_t reg_sdram_rank_size : 2;                    /* bit[15,14].  Choose the size of the rank that the Controller needs to support.
                                                                * 0x0: Support 1 RANK.
                                                                * 0x1: Support 2 RANKs.
                                                                * The user needs to accord to the system request to choose the rank number that the controller needs to support.
                                                                * Default Vale : 0x1  */
                uint32_t  : 16;
        } reg_0x260_b;
    };

    union {
        __IOM uint32_t reg_0x264;
        struct {
            __IOM uint32_t reg_ddrc_col_offset_bit0 : 6;                    /* bit[5,0].  This register is used to control the map between the col[0] and DDR_ADDR.
                                                                * col[0] = DDR_ADDR[reg_ddrc_col_offset_bit0]
                                                                * Default Vale : 0x0  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_col_offset_bit1 : 6;                    /* bit[13,8].  This register is used to control the map between the col[1] and DDR_ADDR.
                                                                * col[1] = DDR_ADDR[reg_ddrc_col_offset_bit1]
                                                                * Default Vale : 0x1  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_col_offset_bit2 : 6;                    /* bit[21,16].  This register is used to control the map between the col[2] and DDR_ADDR.
                                                                * col[2] = DDR_ADDR[reg_ddrc_col_offset_bit2]
                                                                * Default Vale : 0x2  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_col_offset_bit3 : 6;                    /* bit[29,24].  This register is used to control the map between the col[3] and DDR_ADDR.
                                                                * col[3] = DDR_ADDR[reg_ddrc_col_offset_bit3]
                                                                * Default Vale : 0x3  */
                uint32_t  : 2;
        } reg_0x264_b;
    };

    union {
        __IOM uint32_t reg_0x268;
        struct {
            __IOM uint32_t reg_ddrc_col_offset_bit4 : 6;                    /* bit[5,0].  This register is used to control the map between the col[4] and DDR_ADDR.
                                                                * col[4] = DDR_ADDR[reg_ddrc_col_offset_bit4]
                                                                * Default Vale : 0x4  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_col_offset_bit5 : 6;                    /* bit[13,8].  This register is used to control the map between the col[5] and DDR_ADDR.
                                                                * col[5] = DDR_ADDR[reg_ddrc_col_offset_bit5]
                                                                * Default Vale : 0x5  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_col_offset_bit6 : 6;                    /* bit[21,16].  This register is used to control the map between the col[6] and DDR_ADDR.
                                                                * col[6] = DDR_ADDR[reg_ddrc_col_offset_bit6]
                                                                * Default Vale : 0x6  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_col_offset_bit7 : 6;                    /* bit[29,24].  This register is used to control the map between the col[7] and DDR_ADDR.
                                                                * col[7] = DDR_ADDR[reg_ddrc_col_offset_bit7]
                                                                * Default Vale : 0x7  */
                uint32_t  : 2;
        } reg_0x268_b;
    };

    union {
        __IOM uint32_t reg_0x26c;
        struct {
            __IOM uint32_t reg_ddrc_col_offset_bit8 : 6;                    /* bit[5,0].  This register is used to control the map between the col[8] and DDR_ADDR.
                                                                * col[8] = DDR_ADDR[reg_ddrc_col_offset_bit8]
                                                                * Default Vale : 0x8  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_col_offset_bit9 : 6;                    /* bit[13,8].  This register is used to control the map between the col[9] and DDR_ADDR.
                                                                * col[9] = DDR_ADDR[reg_ddrc_col_offset_bit9]
                                                                * Default Vale : 0x9  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_col_offset_bit10 : 6;                    /* bit[21,16].  This register is used to control the map between the col[10] and DDR_ADDR.
                                                                * col[10] = DDR_ADDR[reg_ddrc_col_offset_bit10]
                                                                * Default Vale : 0x0  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_col_offset_bit11 : 6;                    /* bit[29,24].  This register is used to control the map between the col[11] and DDR_ADDR.
                                                                * col[11] = DDR_ADDR[reg_ddrc_col_offset_bit11]
                                                                * Default Vale : 0x0  */
                uint32_t  : 2;
        } reg_0x26c_b;
    };

    union {
        __IOM uint32_t reg_0x270;
        struct {
            __IOM uint32_t reg_ddrc_row_offset_bit0 : 6;                    /* bit[5,0].  This register is used to control the map between the row[0] and DDR_ADDR.
                                                                * row[0] = DDR_ADDR[reg_ddrc_row_offset_bit0]
                                                                * Default Vale : 0xa  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit1 : 6;                    /* bit[13,8].  This register is used to control the map between the row[1] and DDR_ADDR.
                                                                * row[1] = DDR_ADDR[reg_ddrc_row_offset_bit1]
                                                                * Default Vale : 0xb  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit2 : 6;                    /* bit[21,16].  This register is used to control the map between the row[2] and DDR_ADDR.
                                                                * row[2] = DDR_ADDR[reg_ddrc_row_offset_bit2]
                                                                * Default Vale : 0xc  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit3 : 6;                    /* bit[29,24].  This register is used to control the map between the row[3] and DDR_ADDR.
                                                                * row[3] = DDR_ADDR[reg_ddrc_row_offset_bit3]
                                                                * Default Vale : 0xd  */
                uint32_t  : 2;
        } reg_0x270_b;
    };

    union {
        __IOM uint32_t reg_0x274;
        struct {
            __IOM uint32_t reg_ddrc_row_offset_bit4 : 6;                    /* bit[5,0].  This register is used to control the map between the row[4] and DDR_ADDR.
                                                                * row[4] = DDR_ADDR[reg_ddrc_row_offset_bit4]
                                                                * Default Vale : 0xe  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit5 : 6;                    /* bit[13,8].  This register is used to control the map between the row[5] and DDR_ADDR.
                                                                * row[5] = DDR_ADDR[reg_ddrc_row_offset_bit5]
                                                                * Default Vale : 0xf  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit6 : 6;                    /* bit[21,16].  This register is used to control the map between the row[6] and DDR_ADDR.
                                                                * row[6] = DDR_ADDR[reg_ddrc_row_offset_bit6]
                                                                * Default Vale : 0x10  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit7 : 6;                    /* bit[29,24].  This register is used to control the map between the row[7] and DDR_ADDR.
                                                                * row[7] = DDR_ADDR[reg_ddrc_row_offset_bit7]
                                                                * Default Vale : 0x11  */
                uint32_t  : 2;
        } reg_0x274_b;
    };

    union {
        __IOM uint32_t reg_0x278;
        struct {
            __IOM uint32_t reg_ddrc_row_offset_bit8 : 6;                    /* bit[5,0].  This register is used to control the map between the row[8] and DDR_ADDR.
                                                                * row[8] = DDR_ADDR[reg_ddrc_row_offset_bit8]
                                                                * Default Vale : 0x12  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit9 : 6;                    /* bit[13,8].  This register is used to control the map between the row[9] and DDR_ADDR.
                                                                * row[9] = DDR_ADDR[reg_ddrc_row_offset_bit9]
                                                                * Default Vale : 0x13  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit10 : 6;                    /* bit[21,16].  This register is used to control the map between the row[10] and DDR_ADDR.
                                                                * row[10] = DDR_ADDR[reg_ddrc_row_offset_bit10]
                                                                * Default Vale : 0x14  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit11 : 6;                    /* bit[29,24].  This register is used to control the map between the row[11] and DDR_ADDR.
                                                                * row[11] = DDR_ADDR[reg_ddrc_row_offset_bit11]
                                                                * Default Vale : 0x15  */
                uint32_t  : 2;
        } reg_0x278_b;
    };

    union {
        __IOM uint32_t reg_0x27c;
        struct {
            __IOM uint32_t reg_ddrc_row_offset_bit12 : 6;                    /* bit[5,0].  This register is used to control the map between the row[12] and DDR_ADDR.
                                                                * row[12] = DDR_ADDR[reg_ddrc_row_offset_bit12]
                                                                * Default Vale : 0x16  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit13 : 6;                    /* bit[13,8].  This register is used to control the map between the row[13] and DDR_ADDR.
                                                                * row[13] = DDR_ADDR[reg_ddrc_row_offset_bit13]
                                                                * Default Vale : 0x17  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit14 : 6;                    /* bit[21,16].  This register is used to control the map between the row[14] and DDR_ADDR.
                                                                * row[14] = DDR_ADDR[reg_ddrc_row_offset_bit14]
                                                                * Default Vale : 0x18  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit15 : 6;                    /* bit[29,24].  This register is used to control the map between the row[15] and DDR_ADDR.
                                                                * row[15] = DDR_ADDR[reg_ddrc_row_offset_bit15]
                                                                * Default Vale : 0x19  */
                uint32_t  : 2;
        } reg_0x27c_b;
    };

    union {
        __IOM uint32_t reg_0x280;
        struct {
            __IOM uint32_t reg_ddrc_row_offset_bit16 : 6;                    /* bit[5,0].  This register is used to control the map between the row[16] and DDR_ADDR.
                                                                * row[16] = DDR_ADDR[reg_ddrc_row_offset_bit16]
                                                                * Default Vale : 0x0  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_row_offset_bit17 : 6;                    /* bit[13,8].  This register is used to control the map between the row[17] and DDR_ADDR.
                                                                * row[17] = DDR_ADDR[reg_ddrc_row_offset_bit17]
                                                                * Default Vale : 0x0  */
                uint32_t  : 18;
        } reg_0x280_b;
    };

    union {
        __IOM uint32_t reg_0x284;
        struct {
            __IOM uint32_t reg_ddrc_ba_offset_bit0 : 6;                    /* bit[5,0].  This register is used to control the map between the bank[0] and DDR_ADDR.
                                                                * bank[0] = DDR_ADDR[reg_ddrc_bank_offset_bit0]
                                                                * Default Vale : 0x1a  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_ba_offset_bit1 : 6;                    /* bit[13,8].  This register is used to control the map between the bank[1] and DDR_ADDR.
                                                                * bank[1] = DDR_ADDR[reg_ddrc_bank_offset_bit1]
                                                                * Default Vale : 0x1b  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_ba_offset_bit2 : 6;                    /* bit[21,16].  This register is used to control the map between the bank[2] and DDR_ADDR.
                                                                * bank[2] = DDR_ADDR[reg_ddrc_bank_offset_bit2]
                                                                * For DDR4, This register is used to control the map between the bg[0] and DDR_ADDR.
                                                                * bg[0] = DDR_ADDR[reg_ddrc_bank_offset_bit2]
                                                                * Default Vale : 0x1c  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_ba_offset_bit3 : 6;                    /* bit[29,24].  This register is used to control the map between the bank[3] and DDR_ADDR.
                                                                * bank[3] = DDR_ADDR[reg_ddrc_bank_offset_bit3]
                                                                * For DDR4, This register is used to control the map between the bg[1] and DDR_ADDR.
                                                                * bg[1] = DDR_ADDR[reg_ddrc_bank_offset_bit3]
                                                                * Default Vale : 0x0  */
                uint32_t  : 2;
        } reg_0x284_b;
    };

    union {
        __IOM uint32_t reg_0x288;
        struct {
            __IOM uint32_t reg_ddrc_rank_offset_bit0 : 6;                    /* bit[5,0].  This register is used to control the map between the rank[0] and DDR_ADDR.
                                                                * rank[0] = DDR_ADDR[reg_ddrc_rank_offset_bit0]
                                                                * Default Vale : 0x1d  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_rank_offset_bit1 : 6;                    /* bit[13,8].  This register is used to control the map between the rank[1] and DDR_ADDR.
                                                                * rank[1] = DDR_ADDR[reg_ddrc_rank_offset_bit1]
                                                                * Default Vale : 0x1e  */
                uint32_t  : 18;
        } reg_0x288_b;
    };

    __IOM uint32_t reg_0x28c;                /* Reserved.
                                                                * Default Vale : 0x0  */

    union {
        __IOM uint32_t reg_0x290;
        struct {
            __IOM uint32_t reg_ddrc_valid_rank_channel : 4;                    /* bit[3,0].  Used to control the valid rank channel.
                                                                * 2'b01: When the controller needs to support only 1 rank.
                                                                * 2'b11: When the controller needs to support 2 ranks.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_imc_interrupt_mask : 7;                    /* bit[10,4].  The interrupt signal mask of the controller. Active High.
                                                                * When the controller detect error such as the inline ecc for uncorrectable error, the controller can generate the interrupt through the imc_interrutp port. When this bit set to 1, it will mask this interrupt and keep the imc_interrutp port always to be zero. 
                                                                * [0]: Mask the write exaccess fail interrupt.
                                                                * [1]: Mask the dfi low power handshake timeout interrupt. 
                                                                * [2]: Mask the dfi low power handshake fail interrupt.
                                                                * [3]: Mask the ECC uncorrectable interrupt.
                                                                * [4]: Mask the read address out-of-range interrupt.
                                                                * [5]: Mask the write address out-of-range interrupt.
                                                                * [6]: Mask the ECC correctable interrupt.
                                                                * Default Vale : 0x0  */
                uint32_t  : 21;
        } reg_0x290_b;
    };

    union {
        __IOM uint32_t reg_0x294;
        struct {
            __IOM uint32_t reg_dfi_ctrlupd_min_x1024 : 16;                    /* bit[15,0].  This is the minimum amount of time between controller initiated DFI update requests.Set this number higher to reduce the frequency of update requests,.
                                                                * reg_dfi_ctrlupd_min_x1024 >= 0x1.
                                                                * Unit: core_clk * 1024
                                                                * Default Vale : 0x14  */
            __IOM uint32_t reg_dfi_ctrlupd_max_x1024 : 16;                    /* bit[31,16].  This is the maximum amount of time between controller initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the
                                                                * dfi_ctrlupd_ack  is received.
                                                                * reg_dfi_ctrlupd_max_x1024 >= 0x1 and reg_dfi_ctrlupd_max_x1024 > reg_dfi_ctrlupd_min_x1024.
                                                                * Unit: core_clk * 1024
                                                                * Default Vale : 0x26  */
        } reg_0x294_b;
    };

    union {
        __IOM uint32_t reg_0x298;
        struct {
            __IOM uint32_t reg_dfi_ctrlupd_dis : 1;                    /* bit[0].  The disable signal of the ctrl update function. Active High.
                                                                * 1: Disable the automatic dfi_ctrlupd_req generation.
                                                                * 0: Controller will generate dfi_ctrlupd_req periodically.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_ddrc_dfi_ctrlupd_max : 10;                    /* bit[10,1].  Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert.reg_ddrc_dfi_ctrlupd_max >= 0x40.
                                                                * Unit:core_clk
                                                                * Default Vale : 0x40  */
            __IOM uint32_t reg_ddrc_dfi_ctrlupd_min : 10;                    /* bit[20,11].  Specifies the minimum number of dfi clock cycles that the dfi_ctrlupd_req signal must be asserted. The controller expects the PHY to respond within this time. If the PHY does not respond, the controller de-asserts dfi_ctrlupd_req after reg_ddrc_dfi_ctrlup_min cycles.
                                                                * reg_ddrc_dfi_ctrlupd_min >= 0x1.
                                                                * Unit: core clk
                                                                * Default Vale : 0x8  */
                uint32_t  : 11;
        } reg_0x298_b;
    };

    __IOM uint32_t reg_0x29c;                /* This is the period amount of time between controller initiated DFI update requests. This timer resets with each osc request; when the timer expires the osc flow will generate.
                                                                * reg_ddrc_dqsosc_period_x1024 >= 0x1. Only for LPDDR5.
                                                                * Default Vale : 0x100  */

    union {
        __IOM uint32_t reg_0x2a0;
        struct {
            __IOM uint32_t reg_lpddr5_dqsosc_wck2dqo_en : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddr5_dqsosc_wck2dqi_en : 1;                    /* bit[1].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddr5_dqsosc_stop_auto : 1;                    /* bit[2].  Reserved.
                                                                * Default Vale : 0x0  */
                uint32_t  : 5;
            __IOM uint32_t reg_lpddr5_dqsosc_wck2dqo_interval : 8;                    /* bit[15,8].  Reserved.
                                                                * Default Vale : 0x80  */
            __IOM uint32_t reg_lpddr5_dqsosc_wck2dqi_interval : 8;                    /* bit[23,16].  Reserved.
                                                                * Default Vale : 0x80  */
                uint32_t  : 8;
        } reg_0x2a0_b;
    };

    union {
        __IOM uint32_t reg_0x2a4;
        struct {
            __IOM uint32_t reg_tpbr2act : 8;                    /* bit[7,0].  The register is used to control the timing parameter tpbr2act.
                                                                * Default Vale : 0x10  */
            __IOM uint32_t reg_tpbr2pbr : 8;                    /* bit[15,8].  The register is used to control th timing parameter tpbr2ptr.
                                                                * Default Vale : 0x10  */
                uint32_t  : 16;
        } reg_0x2a4_b;
    };

    union {
        __IOM uint32_t reg_0x2a8;
        struct {
            __IOM uint32_t reg_rfm_user_raammt_en : 1;                    /* bit[1].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rfm_mode_reg_en : 1;                    /* bit[2].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_user_mrr_data_en_to_rfm : 1;                    /* bit[3].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rfm_en : 1;                    /* bit[4].  Reserved.
                                                                * Default Vale : 0x0  */
                uint32_t  : 27;
        } reg_0x2a8_b;
    };

    __IOM uint32_t reg_0x2ac;                /* Reserved.
                                                                * Default Vale : 0x100  */

    union {
        __IOM uint32_t reg_0x2b0;
        struct {
            __IOM uint32_t reg_rfm_mode_register27 : 16;                    /* bit[15,0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rfm_mode_register57 : 16;                    /* bit[31,16].  Reserved.
                                                                * Default Vale : 0x0  */
        } reg_0x2b0_b;
    };

    __IOM uint32_t reg_0x2b4;                /* Reserved.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x2b8;                /* Reserved.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x2bc;                /* Reserved.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x2c0;                /* Reserved.
                                                                * Default Vale : 0x0  */

    union {
        __IOM uint32_t reg_0x2c4;
        struct {
            __IOM uint32_t reg_imc_dpr_key_info : 22;                    /* bit[21,0].  Reserved.
                                                                * Default Vale : 0x0  */
                uint32_t  : 8;
            __IOM uint32_t reg_imc_dpr_lut_clr : 1;                    /* bit[30].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_imc_dpr_lut_update : 1;                    /* bit[31].  Reserved.
                                                                * Default Vale : 0x0  */
        } reg_0x2c4_b;
    };

    __IOM uint32_t reg_0x2c8;                /* Reserved.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x2cc;                /* Reserved.
                                                                * Default Vale : 0x0  */

    union {
        __IOM uint32_t reg_0x2d0;
        struct {
            __IOM uint32_t reg_pageclose_en : 1;                    /* bit[0].  When the reg_pageclose_en = 1'b1 && reg_pageclose_timer == 8'h0, the controller generates the auto-precharge write or auto precharge read command at the last page open write or read operation in the command queue to close that open bank.
                                                                * When the reg_pageclse_en = 1'b1 && reg_pageclse_timer > 8'h0, the controller will wait for the delay setting by the reg_pageclose_timer after to last page open write or read operation in the command queue to generate the precharge command to close that open bank.
                                                                * When the delay setting is smaller than the (reg_twtp/2) or (reg_trtp/2), the controller will accord to the reg_twtp and reg_trtp to generate the precharge to close the open bank.
                                                                * Delay Unit: Tcore_clk
                                                                * Note: When the reg_pageclose_timer != 8'h0 and disable the auto precharge function, the reg_page_close_timer > (reg_tccd/2), or it will influence the efficiency of the SDRAM.
                                                                * Default Vale : 0x1  */
                uint32_t  : 7;
            __IOM uint32_t reg_pageclose_timer : 8;                    /* bit[15,8].  When the reg_pageclose_en = 1'b1 && reg_pageclose_timer == 8'h0, the controller generates the auto-precharge write or auto precharge read command at the last page open write or read operation in the command queue to close that open bank.
                                                                * When the reg_pageclse_en = 1'b1 && reg_pageclse_timer > 8'h0, the controller will wait for the delay setting by the reg_pageclose_timer after to last page open write or read operation in the command queue to generate the precharge command to close that open bank.
                                                                * When the delay setting is smaller than the (reg_twtp/2) or (reg_trtp/2), the controller will accord to the reg_twtp and reg_trtp to generate the precharge to close the open bank.
                                                                * Delay Unit: Tcore_clk
                                                                * Note: When the reg_pageclose_timer != 8'h0 and disable the auto precharge function, the reg_page_close_timer > (reg_tccd/2), or it will influence the efficiency of the SDRAM.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_wdbi_en : 1;                    /* bit[16].  The write DBI enable signal of the controller of the DDR4 or LPDDR4.
                                                                * 0:Dsiable the write DBI function.
                                                                * 1:Enable the write DBI function of the DDR4.
                                                                * When choose the DDR4 mode and enable the DBI mode:
                                                                * 1) The data of each byte and the corresponding dm signal will equal or more than 5 bits "1"
                                                                * 2) Can't support the data mask function directly, the controller will use the RMW operation to complete the data mask operation.
                                                                * 
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddr4_rdbi_en : 1;                    /* bit[17].  The read dbi enable signal of the DDR4. Active High. 
                                                                * When the user enable the RDBI function of the DDR4 SDRAM by setting the MR5[12] to 1'b1, this bit should set to 1'b1.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_rmw_en : 1;                    /* bit[18].  The read modify write operation enable signal of the DDR3. Active High. 
                                                                * When enable this signal, the controller will generate the read modify write command when need mask operation.
                                                                * Default Vale : 0x0  */
                uint32_t  : 13;
        } reg_0x2d0_b;
    };

    union {
        __IOM uint32_t reg_0x2d4;
        struct {
            __IOM uint32_t reg_auto_ref_gen : 1;                    /* bit[0].  The generate signal of the auto refresh. Posedge will be valid.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_auto_ref_mode : 1;                    /* bit[1].  Choose the auto refresh mode.
                                                                * 1: Gnerate the auto refresh each tREFI time interval.
                                                                * 0: Enable the burst mode. The controler will accord to the setting of the reg_ddrc_auto_ref_burst to keep the auto-refresh command, when the number of the auto-refresh number equals to the reg_ddrc_auto_ref_burst, it will use the burst to send the auto-refresh successively.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_ddrc_auto_ref_dis : 1;                    /* bit[2].  The disable signal of the auto refresh. Active High.
                                                                * 1 Disable the auto refresh function, then the controller will stop to send the auto refresh.
                                                                * 0: Enable the auto frefresh function, then the controller will auto generate the auto refresh based on the sdram specification.
                                                                * Default Vale : 0x0  */
                uint32_t  : 5;
            __IOM uint32_t reg_ddrc_auto_ref_pre_margin : 8;                    /* bit[15,8].  Reserved.
                                                                * Default Vale : 0x1f  */
            __IOM uint32_t reg_ddrc_auto_ref_burst : 3;                    /* bit[18,16].  Used to control the burst number of the auto refresh when the reg_ddrc_auto_ref_mode = 1'b0.
                                                                * Default Vale : 0x3  */
                uint32_t  : 13;
        } reg_0x2d4_b;
    };

    union {
        __IOM uint32_t reg_0x2d8;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode01 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * DDR23 corresponding to MR3 ;
                                                                * LPDDR23 corresponding to MR2 ;
                                                                * DDR4 corresponding to MR6 ; 
                                                                * LPDDR4 corresponding to MR1 of fsp0 and rank1
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode00 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * DDR23 corresponding to MR2 ;
                                                                * LPDDR23 corresponding to MR1 ;
                                                                * DDR4 corresponding to MR3 ; 
                                                                * LPDDR4 corresponding to MR13 of fsp0 and rank1
                                                                * Default Vale : 0x0  */
        } reg_0x2d8_b;
    };

    union {
        __IOM uint32_t reg_0x2dc;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode03 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * DDR23 corresponding to MR0 ;
                                                                * DDR4 corresponding to MR4 ; 
                                                                * LPDDR4 corresponding to MR3 of fsp0 and rank1
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode02 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * DDR23 corresponding to MR1 ;
                                                                * LPDDR23 corresponding to MR3 ;
                                                                * DDR4 corresponding to MR5 ; 
                                                                * LPDDR4 corresponding to MR2 of fsp0 and rank1
                                                                * Default Vale : 0x0  */
        } reg_0x2dc_b;
    };

    union {
        __IOM uint32_t reg_0x2e0;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode05 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * DDR4 corresponding to MR1 ; 
                                                                * LPDDR4 corresponding to MR14 of fsp0 and rank1
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode04 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * DDR4 corresponding to MR2 ; 
                                                                * LPDDR4 corresponding to MR11 of fsp0 and rank1
                                                                * Default Vale : 0x0  */
        } reg_0x2e0_b;
    };

    union {
        __IOM uint32_t reg_0x2e4;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode07 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * LPDDR4 corresponding to MR13 of fsp1 and rank1
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode06 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * DDR4 corresponding to MR0 ; 
                                                                * LPDDR4 corresponding to MR22 of fsp0 and rank1
                                                                * Default Vale : 0x0  */
        } reg_0x2e4_b;
    };

    union {
        __IOM uint32_t reg_0x2e8;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode09 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * LPDDR4 corresponding to MR2 of fsp1 and rank1
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode08 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * LPDDR4 corresponding to MR1 of fsp1 and rank1
                                                                * Default Vale : 0x0  */
        } reg_0x2e8_b;
    };

    union {
        __IOM uint32_t reg_0x2ec;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode11 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * LPDDR4 corresponding to MR11 of fsp1 and rank1
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode10 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * LPDDR4 corresponding to MR3 of fsp1 and rank1
                                                                * Default Vale : 0x0  */
        } reg_0x2ec_b;
    };

    union {
        __IOM uint32_t reg_0x2f0;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode13 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * LPDDR4 corresponding to MR22 of fsp1 and rank1
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode12 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * LPDDR4 corresponding to MR14 of fsp1 and rank1
                                                                * Default Vale : 0x0  */
        } reg_0x2f0_b;
    };

    union {
        __IOM uint32_t reg_0x2f4;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode15 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR15 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode14 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR of LPDDRn/DDRn at sdram initialization state. 
                                                                * LPDDR4 corresponding to MR13 of fsp1 and rank1
                                                                * Default Vale : 0x0  */
        } reg_0x2f4_b;
    };

    union {
        __IOM uint32_t reg_0x2f8;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode17 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR17 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode16 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR16 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x2f8_b;
    };

    union {
        __IOM uint32_t reg_0x2fc;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode19 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR19 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode18 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR18 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x2fc_b;
    };

    union {
        __IOM uint32_t reg_0x300;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode21 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR21 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode20 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR20 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x300_b;
    };

    union {
        __IOM uint32_t reg_0x304;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode23 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR23 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode22 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR22 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x304_b;
    };

    union {
        __IOM uint32_t reg_0x308;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode25 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR25 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode24 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR24 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x308_b;
    };

    union {
        __IOM uint32_t reg_0x30c;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode27 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR27 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode26 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR26 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x30c_b;
    };

    union {
        __IOM uint32_t reg_0x310;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode29 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR29 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode28 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR28 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x310_b;
    };

    union {
        __IOM uint32_t reg_0x314;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode31 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode30 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR30 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x314_b;
    };

    union {
        __IOM uint32_t reg_0x318;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode33 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode32 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x318_b;
    };

    union {
        __IOM uint32_t reg_0x31c;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode35 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode34 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x31c_b;
    };

    union {
        __IOM uint32_t reg_0x320;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode37 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode36 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x320_b;
    };

    union {
        __IOM uint32_t reg_0x324;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode39 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode38 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x324_b;
    };

    union {
        __IOM uint32_t reg_0x328;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode41 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode40 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x328_b;
    };

    union {
        __IOM uint32_t reg_0x32c;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode43 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode42 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x32c_b;
    };

    union {
        __IOM uint32_t reg_0x330;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode45 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode44 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x330_b;
    };

    union {
        __IOM uint32_t reg_0x334;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode47 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode46 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x334_b;
    };

    union {
        __IOM uint32_t reg_0x338;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode49 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode48 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x338_b;
    };

    union {
        __IOM uint32_t reg_0x33c;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode51 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode50 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x33c_b;
    };

    union {
        __IOM uint32_t reg_0x340;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode53 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode52 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x340_b;
    };

    union {
        __IOM uint32_t reg_0x344;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode55 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode54 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x344_b;
    };

    union {
        __IOM uint32_t reg_0x348;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode57 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode56 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x348_b;
    };

    union {
        __IOM uint32_t reg_0x34c;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode59 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode58 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x34c_b;
    };

    union {
        __IOM uint32_t reg_0x350;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode61 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode60 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x350_b;
    };

    union {
        __IOM uint32_t reg_0x354;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode63 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode62 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x354_b;
    };

    union {
        __IOM uint32_t reg_0x358;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode65 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode64 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x358_b;
    };

    union {
        __IOM uint32_t reg_0x35c;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode67 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode66 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x35c_b;
    };

    union {
        __IOM uint32_t reg_0x360;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode69 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode68 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x360_b;
    };

    union {
        __IOM uint32_t reg_0x364;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode71 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode70 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x364_b;
    };

    union {
        __IOM uint32_t reg_0x368;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode73 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode72 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x368_b;
    };

    union {
        __IOM uint32_t reg_0x36c;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode75 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode74 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x36c_b;
    };

    union {
        __IOM uint32_t reg_0x370;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode77 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode76 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x370_b;
    };

    union {
        __IOM uint32_t reg_0x374;
        struct {
            __IOM uint32_t reg_lpddrn_ddrn_load_mode79 : 16;                    /* bit[15,0].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddrn_ddrn_load_mode78 : 16;                    /* bit[31,16].  The register related to the lpddrn/ddrn initialization. This register is used to control the value which will be written to the MR31 of LPDDRn/DDRn at sdram initialization state.
                                                                * Default Vale : 0x0  */
        } reg_0x374_b;
    };

    union {
        __IOM uint32_t reg_0x378;
        struct {
            __IOM uint32_t reg_bufferen_core : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_dfi_idle_en : 1;                    /* bit[1].  Reserved
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_lpddr4_modevref_bp : 1;                    /* bit[2].  Reserved.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_lpddr4_tccdmw_bp : 1;                    /* bit[3].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t mrr_dai : 1;                    /* bit[4].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_addr_remap_en : 1;                    /* bit[5].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_exa_fail_flag_clear : 1;                    /* bit[6].  The write exacess flag clear signal. Active High. 
                                                                * Default Vale : 0x0  */
                uint32_t  : 1;
            __IOM uint32_t reg_mrwreset_1us : 8;                    /* bit[15,8].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_mrr_pulse : 8;                    /* bit[23,16].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_dfi_frequency : 5;                    /* bit[28,24].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_waddr_out_of_range_clear : 1;                    /* bit[29].  The interrupt imc_interrupt_waddr_out_of_range clear signal. Active High. When this signal changes to high, it will set the imc_interrupt_waddr_out_of_range clear to 1'b0.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_raddr_out_of_range_clear : 1;                    /* bit[30].  The interrupt imc_interrupt_raddr_out_of_range clear signal. Active High. When this signal changes to high, it will set the imc_interrupt_raddr_out_of_range clear to 1'b0.
                                                                * Default Vale : 0x0  */
                uint32_t  : 1;
        } reg_0x378_b;
    };

    __IOM uint32_t reg_0x37c;                /* Reserved.
                                                                * Default Vale : 0xff  */

    union {
        __IOM uint32_t reg_0x380;
        struct {
            __IOM uint32_t reg_lpddr45_derated_en : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_lpddr45_derated_pause : 1;                    /* bit[1].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_mr4_tuf_dis : 1;                    /* bit[2].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_derated_trefi_x0p125_dis : 1;                    /* bit[3].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_derated_trefi_x6x8_dis : 1;                    /* bit[4].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_derated_limit_exceed_intr_clr : 1;                    /* bit[5].  Reserved.
                                                                * Default Vale : 0x0  */
                uint32_t  : 2;
            __IOM uint32_t reg_mrr_active_byte_rank0 : 4;                    /* bit[11,8].  Reserved.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_mrr_active_byte_rank1 : 4;                    /* bit[15,12].  Reserved.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_mrr_active_byte_rank2 : 4;                    /* bit[19,16].  Reserved.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_mrr_active_byte_rank3 : 4;                    /* bit[23,20].  Reserved.
                                                                * Default Vale : 0x1  */
                uint32_t  : 8;
        } reg_0x380_b;
    };

    union {
        __IM uint32_t reg_0x384;
        struct {
            __IM uint32_t phy_init_complete_to_reg : 1;                    /* bit[0].  The done signal of the phy initialization after ther reg_phy_init_start to high. Active high.
                                                                * When this bit changes to high after the set the reg_phy_init_start to high, it means that the controller compeltes the initialization of the SDRAM.
                                                                * Default Vale : 0x0  */
            __IM uint32_t sdram_init_done_to_reg : 1;                    /* bit[1].  The done signal of the sdram initialization after set the reg_ddrc_init_start to high. Active high.
                                                                * When this bit changes to high after set the reg_ddrc_init_start to high, it means that the controller completes the initialization of the SDRAM.
                                                                * Default Vale : 0x0  */
                uint32_t  : 1;
            __IM uint32_t ddrc_init_act : 1;                    /* bit[3].  The controller is doint the sdram initialization. Active High.
                                                                * Default Vale : 0x0  */
            __IM uint32_t exa_int_exa_fail_to_reg : 1;                    /* bit[4].  The write exaccess fail flag. Active High.
                                                                * This flag can be cleared by set the reg_exa_fail_flag_clear to high.
                                                                * Default Vale : 0x0  */
                uint32_t  : 24;
            __IM uint32_t reg_dfi_lp_exit_handshake_timeout : 1;                    /* bit[29].  The dfi low power interface hand shake timeout flag. Active High.
                                                                * It wil generate the interrup through the imc_interrupt port.
                                                                * Default Vale : 0x0  */
            __IM uint32_t reg_dfi_lp_entry_handshake_fail : 1;                    /* bit[30].  The dfi low power interface hand shake fail flag. Active High.
                                                                * It wil generate the interrup through the imc_interrupt port.
                                                                * Default Vale : 0x0  */
                uint32_t  : 1;
        } reg_0x384_b;
    };

    union {
        __IM uint32_t reg_0x388;
        struct {
            __IM uint32_t reg_bist_done : 1;                    /* bit[0].  The MEM-BIST compelte signal. Ative high.
                                                                * Default Vale : 0x0  */
            __IM uint32_t reg_bist_pass : 1;                    /* bit[1].  The MEM-BIST pass signal. Active high. Valid when the reg_bist_done is high.
                                                                * Default Vale : 0x0  */
                uint32_t  : 2;
            __IM uint32_t reg_bist_state : 7;                    /* bit[10,4].  The obs signal of the FSM using to control the data path. Just for debug.
                                                                * Default Vale : 0x1  */
                uint32_t  : 5;
            __IM uint32_t reg_data_bist_state : 7;                    /* bit[22,16].  The obs signal of the FSM using to control the data path. Just for debug.
                                                                * Default Vale : 0x1  */
                uint32_t  : 1;
            __IM uint32_t reg_bist_error_cnt : 8;                    /* bit[31,24].  The error counter in whole MEM-BIST.
                                                                * Default Vale : 0x0  */
        } reg_0x388_b;
    };

    __IM uint32_t reg_0x38c;                /* When the MEM-BIST meets error, this register will store the error address information for bit[31:0].
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x390;                /* Reserved.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x394;                /* Reserved.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x398;                /* When the MEM-BIST meets error, this register will store the actual read back data of the beat7 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x39c;                /* When the MEM-BIST meets error, this register will store the actual read back data of the beat6 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3a0;                /* When the MEM-BIST meets error, this register will store the actual read back data of the beat5 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3a4;                /* When the MEM-BIST meets error, this register will store the actual read back data of the beat4 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3a8;                /* Reserved.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3ac;                /* Reserved.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3b0;                /* When the MEM-BIST meets error, this register will store the expect read back data of the beat7 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3b4;                /* When the MEM-BIST meets error, this register will store the expect read back data of the beat6 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3b8;                /* When the MEM-BIST meets error, this register will store the expect read back data of the beat5 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3bc;                /* When the MEM-BIST meets error, this register will store the expect read back data of the beat4 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3c0;                /* When the MEM-BIST meets error, this register will store the actual read back data of the beat3 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3c4;                /* When the MEM-BIST meets error, this register will store the actual read back data of the beat2 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3c8;                /* When the MEM-BIST meets error, this register will store the actual read back data of the beat1 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3cc;                /* When the MEM-BIST meets error, this register will store the actual read back data of the beat0 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3d0;                /* When the MEM-BIST meets error, this register will store the expect read back data of the beat3 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3d4;                /* When the MEM-BIST meets error, this register will store the expect read back data of the beat2 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3d8;                /* When the MEM-BIST meets error, this register will store the expect read back data of the beat1 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3dc;                /* When the MEM-BIST meets error, this register will store the expect read back data of the beat0 in the read burst 8.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3e0;                /* The register show the bit lines corrected. For DQ32, there are 32 bit lines, when there is a corrected error for one the bit lines, the corresponding bit will set to high.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3e4;                /* The register show the bit lines corrected by single-bit ECC error. For DQ32, there are 32 bit lines, when there is a corrected error for one the bit lines, the corresponding bit will set to high.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3e8;                /* The register show the bit lines corrected by single-bit ECC error. For DQ32, there are 32 bit lines, when there is a corrected error for one the bit lines, the corresponding bit will set to high.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3ec;                /* The number of detecting uncorrectable ECC errors. This register value will be clean when the reg_ddrc_ecc_uncorr_err_cnt_clr set to 1.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x3f0;                /* The number of detecting correctable ECC errors. This register value will be clean when the reg_ddrc_ecc_corr_err_cnt_clr set to 1.
                                                                * Default Vale : 0x0  */

    union {
        __IM uint32_t reg_0x3f4;
        struct {
            __IM uint32_t reg_ddrc_ecc_uncorr_err_bank : 4;                    /* bit[3,0].  The bank number of the read address when a uncorrected ECC error occours. 
                                                                * When the IMC chooses DDR3 mode, the bank[2:0] means the bank number.
                                                                * When the IMC chooses DDR4 mode, the bank[1:0] means the bank number, the bank[3:2] means the bank group number.
                                                                * Default Vale : 0x0  */
            __IM uint32_t reg_ddrc_ecc_uncorr_err_rank : 1;                    /* bit[4].  The rank number of the read address when a uncorrected ECC error occours.
                                                                * Default Vale : 0x0  */
                uint32_t  : 3;
            __IM uint32_t reg_ddrc_ecc_corr_err : 4;                    /* bit[11,8].  corrected error indicators. Active High.
                                                                * Bit3: The sdram Beat 3 has corrected errors.
                                                                * Bit2: The sdram Beat 2 has corrected errors.
                                                                * Bit1: The sdram Beat 1 has corrected errors.
                                                                * Bit0: The sdram Beat 0 has corrected errors.
                                                                * Please reference to the Figure 4-6 to get the concept sdram Beat n.
                                                                * Default Vale : 0x0  */
            __IM uint32_t reg_ddrc_ecc_uncorr_err : 4;                    /* bit[15,12].  Uncorrected error indicators. Active High.
                                                                * Bit3: The sdram Beat 3 has uncorrected errors.
                                                                * Bit2: The sdram Beat 2 has uncorrected errors.
                                                                * Bit1: The sdram Beat 1 has uncorrected errors.
                                                                * Bit0: The sdram Beat 0 has uncorrected errors.
                                                                * Please reference to the Figure 4-6 to get the concept sdram Beat n.
                                                                * Default Vale : 0x0  */
                uint32_t  : 16;
        } reg_0x3f4_b;
    };

    union {
        __IM uint32_t reg_0x3f8;
        struct {
            __IM uint32_t reg_ddrc_ecc_uncorr_err_col : 12;                    /* bit[11,0].  The col number of the read address when a uncorrected ECC error occours.
                                                                * Default Vale : 0x0  */
            __IM uint32_t reg_ddrc_ecc_uncorr_err_row : 17;                    /* bit[28,12].  The row number of the read address when a uncorrected ECC error occours.
                                                                * Default Vale : 0x0  */
                uint32_t  : 3;
        } reg_0x3f8_b;
    };

    union {
        __IM uint32_t reg_0x3fc;
        struct {
            __IM uint32_t reg_ddrc_ecc_corr_err_bank : 4;                    /* bit[3,0].  The bank number of the read address when a corrected ECC error occours. 
                                                                * When the IMC chooses DDR3 mode, the bank[2:0] means the bank number.
                                                                * When the IMC chooses DDR4 mode, the bank[1:0] means the bank number, the bank[3:2] means the bank group number.
                                                                * Default Vale : 0x0  */
            __IM uint32_t reg_ddrc_ecc_corr_err_rank : 1;                    /* bit[4].  The rank number of the read address when a corrected ECC error occours.
                                                                * Default Vale : 0x0  */
                uint32_t  : 27;
        } reg_0x3fc_b;
    };

    union {
        __IM uint32_t reg_0x400;
        struct {
            __IM uint32_t reg_ddrc_ecc_corr_err_col : 12;                    /* bit[11,0].  The col number of the read address when a corrected ECC error occours.
                                                                * Default Vale : 0x0  */
            __IM uint32_t reg_ddrc_ecc_corr_err_row : 17;                    /* bit[28,12].  The row number of the read address when a corrected ECC error occours.
                                                                * Default Vale : 0x0  */
                uint32_t  : 3;
        } reg_0x400_b;
    };

    __IM uint32_t reg_0x404;                /* The exp data when the corrected error occours. Valid when the reg_ddrc_ecc_corr_err_cnt is not zero.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x408;                /* The exp data when the corrected error occours. Valid when the reg_ddrc_ecc_corr_err_cnt is not zero.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x40c;                /* The actual data when the corrected error occours. Valid when the reg_ddrc_ecc_corr_err_cnt is not zero.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x410;                /* The actual data when the corrected error occours. Valid when the reg_ddrc_ecc_corr_err_cnt is not zero.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x414;                /* [0]: The flag shows the user load mode request state.
                                                                *       1: The controller is dealing with the user load mode request.
                                                                *       0: The controller has dealed with the user load mode request.
                                                                * [10:8]: The user load mode main fsm state.
                                                                * [18:16]: The user load mode generate fsm state.
                                                                * Default Vale : 0x0  */

    union {
        __IM uint32_t reg_0x418;
        struct {
            __IM uint32_t core_cmd_empty_to_reg : 1;                    /* bit[0].  The command empty flag of the controller core. Active High.
                                                                * 1: Means there are no pending command in the core. For the write command, the write data has send to the SDRAM following the command; for the read command, the read data has come back.
                                                                * 0: Means there are pending command in the core. 
                                                                * This register should be 1 after the reset value.
                                                                * Default Vale : 0x1  */
                uint32_t  : 3;
            __IM uint32_t pd_fsm_cs_to_reg : 3;                    /* bit[6,4].  The obs register to show the state of the precharge power down state machine. Just use for debug.
                                                                * If the user wants to use the register ( set the reg_slm_ppd_req to high ) to make the SDRAM go into the power-down state, this register should be 2'b00 or 2'b01.
                                                                * Default Vale : 0x0  */
                uint32_t  : 1;
            __IM uint32_t sr_fsm_cs_to_reg : 3;                    /* bit[10,8].  The obs register to show the state of the self-refresh state machine. Just use for debug.
                                                                * If the user wants to use the register  ( set the reg_slm_srf_req to high )  to go into the self-refresh state, this register should be 2'b00 or 2'b01. 
                                                                * Default Vale : 0x0  */
                uint32_t  : 1;
            __IM uint32_t imc_gs_fsm_to_reg : 6;                    /* bit[17,12].  The obs register to show the state of the global schedule state machine. Just for debug.
                                                                * Tis register should be zero after the reset state.
                                                                * Default Vale : 0x0  */
            __IM uint32_t cif_full_state_to_reg : 5;                    /* bit[22,18].  The status register of the command queue and core interface fifo.
                                                                * [0]: Reserved.
                                                                * [1]: Read command queue full state. Active High.
                                                                * [2]: Write ECC command queue full state. Active High. 
                                                                * [3]: Write command queue full state. Active High.
                                                                * [4]: Core interface fifo full state. Active High.
                                                                * Default Vale : 0x0  */
            __IM uint32_t imc_interrupt_to_reg : 1;                    /* bit[23].  The interrupt signal of the controller. When this signal changes to high, it means an interrupt occrus. Then the user can check the {waddr_in_out_of_range_to_reg, raddr_in_out_of_range_to_reg, reg_ddrc_ecc_uncorr_err_cnt, reg_ddrc_ecc_corr_err_cnt,reg_dfi_lp_entry_handshake_fail, reg_dfi_lp_exit_handshake_timeout,exa_int_exa_fail_to_reg} to check the interrutp event.
                                                                * Default Vale : 0x0  */
                uint32_t  : 8;
        } reg_0x418_b;
    };

    __IM uint32_t reg_0x41c;                /* Related to ddr efficiency caculated,at the first caculated period ,ddr controller issue the numbers of write command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x420;                /* Related to ddr efficiency caculated,at the first caculated period ,ddr controller issue the numbers of read command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x424;                /* Related to ddr efficiency caculated,at the second caculated period ,ddr controller issue the numbers of write command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x428;                /* Related to ddr efficiency caculated,at the second caculated period ,ddr controller issue the numbers of read command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x42c;                /* Related to ddr efficiency caculated,at the third caculated period ,ddr controller issue the numbers of write command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x430;                /* Related to ddr efficiency caculated,at the third caculated period ,ddr controller issue the numbers of read command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x434;                /* Related to ddr efficiency caculated,at the fourth caculated period ,ddr controller issue the numbers of write command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x438;                /* Related to ddr efficiency caculated,at the fourth caculated period ,ddr controller issue the numbers of read command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x43c;                /* Related to ddr efficiency caculated,at the fiveth caculated period ,ddr controller issue the numbers of write command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x440;                /* Related to ddr efficiency caculated,at the fiveth caculated period ,ddr controller issue the numbers of read command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x444;                /* Related to ddr efficiency caculated,at the sixth caculated period ,ddr controller issue the numbers of write command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x448;                /* Related to ddr efficiency caculated,at the sixth caculated period ,ddr controller issue the numbers of read command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x44c;                /* Related to ddr efficiency caculated,at the seventh caculated period ,ddr controller issue the numbers of write command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x450;                /* Related to ddr efficiency caculated,at the seventh caculated period ,ddr controller issue the numbers of read command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x454;                /* Related to ddr efficiency caculated,at the eighth caculated period ,ddr controller issue the numbers of write command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x458;                /* Related to ddr efficiency caculated,at the eighth caculated period ,ddr controller issue the numbers of read command.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x45c;                /* 1:MRR data can be read
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x460;                /* MRR data of the mode register set in reg_user_load_mode_value_m0_r0
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x464;                /* MRR data of the mode register set in reg_user_load_mode_value_m1_r0
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x468;                /* MRR data of the mode register set in reg_user_load_mode_value_m2_r0
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x46c;                /* MRR data of the mode register set in reg_user_load_mode_value_m3_r0
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x470;                /* MRR data of the mode register set in reg_user_load_mode_value_m4_r0
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x474;                /* MRR data of the mode register set in reg_user_load_mode_value_m5_r0
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x478;                /* MRR data of the mode register set in reg_user_load_mode_value_m6_r0
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x47c;                /* MRR data of the mode register set in reg_user_load_mode_value_m7_r0
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x480;                /* MRR data of the mode register set in reg_user_load_mode_value_m0_r1
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x484;                /* MRR data of the mode register set in reg_user_load_mode_value_m1_r1
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x488;                /* MRR data of the mode register set in reg_user_load_mode_value_m2_r1
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x48c;                /* MRR data of the mode register set in reg_user_load_mode_value_m3_r1
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x490;                /* MRR data of the mode register set in reg_user_load_mode_value_m4_r1
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x494;                /* MRR data of the mode register set in reg_user_load_mode_value_m5_r1
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x498;                /* MRR data of the mode register set in reg_user_load_mode_value_m6_r1
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x49c;                /* MRR data of the mode register set in reg_user_load_mode_value_m7_r1
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4a0;                /* MRR data of the mode register set in reg_user_load_mode_value_m0_r2
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4a4;                /* MRR data of the mode register set in reg_user_load_mode_value_m1_r2
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4a8;                /* MRR data of the mode register set in reg_user_load_mode_value_m2_r2
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4ac;                /* MRR data of the mode register set in reg_user_load_mode_value_m3_r2
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4b0;                /* MRR data of the mode register set in reg_user_load_mode_value_m4_r2
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4b4;                /* MRR data of the mode register set in reg_user_load_mode_value_m5_r2
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4b8;                /* MRR data of the mode register set in reg_user_load_mode_value_m6_r2
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4bc;                /* MRR data of the mode register set in reg_user_load_mode_value_m7_r2
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4c0;                /* MRR data of the mode register set in reg_user_load_mode_value_m0_r3
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4c4;                /* MRR data of the mode register set in reg_user_load_mode_value_m1_r3
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4c8;                /* MRR data of the mode register set in reg_user_load_mode_value_m2_r3
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4cc;                /* MRR data of the mode register set in reg_user_load_mode_value_m3_r3
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4d0;                /* MRR data of the mode register set in reg_user_load_mode_value_m4_r3
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4d4;                /* MRR data of the mode register set in reg_user_load_mode_value_m5_r3
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4d8;                /* MRR data of the mode register set in reg_user_load_mode_value_m6_r3
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4dc;                /* MRR data of the mode register set in reg_user_load_mode_value_m7_r3
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4e0;                /* The read pending command in the low 32 cells of the read command queue. Active High.High means the read ecc command pending. The pending read ecc command numbers equals the number of "1".
                                                                * This register should be zero after the reset state. It also should be zero after complete the read operation on the slave interface.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4e4;                /* The read pending command in the high 32 cells of the read command queue. Active High.High means the read ecc command pending. The pending read ecc command numbers equals the number of "1".
                                                                * This register should be zero after the reset state. It also should be zero after complete the read operation on the slave interface.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4e8;                /* The write pending command in the low 32 cells of the write command queue. Active High.High means the read ecc command pending. The pending read ecc command numbers equals the number of "1".
                                                                * This register should be zero after the reset state. It also should be zero after complete the write operation on the slave interface and wait for 100 tCLK.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4ec;                /* The write pending command in the high 32 cells of the write command queue. Active High.High means the read ecc command pending. The pending read ecc command numbers equals the number of "1".
                                                                * This register should be zero after the reset state. It also should be zero after complete the write operation on the slave interface and wait for 100 tCLK.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4f0;                /* This register shows the pending write ecc command in the write ecc command queue . High means the write ecc command pending. The pending write ecc command numbers equals the number of "1".
                                                                * This register should be zero after the reset state. It also should be zero after complete the write operation on the slave interface.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4f4;                /* This register shows the pending read ecc command in the low 32 cells of the read command queue . High means the read ecc command pending. The pending read ecc command numbers equals the number of "1".
                                                                * This register should be zero after the reset state. It also should be zero after complete the read operation on the slave interface.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x4f8;                /* This register shows the pending read ecc command in the high 32 cells of the read command queue. High means the read ecc command pending. The pending read ecc command numbers equals the number of "1".
                                                                * This register should be zero after the reset state. It also should be zero after complete the read operation on the slave interface.
                                                                * Default Vale : 0x0  */

    union {
        __IM uint32_t reg_0x4fc;
        struct {
            __IM uint32_t rank0_auto_ref_cs_to_reg : 4;                    /* bit[3,0].  The auto refresh state of the rank0.
                                                                * When rank0_auto_ref_cs_to_reg = 4'h1, it means the auto refresh state machine is in idle state.
                                                                * If the user uses the reg_ddrc_auto_ref_dis set to 1 to disable the auto refresh function, it should wait for this register change to 4'h1 to excute the next step. 
                                                                * eg. If the user needs to close the auto-refresh operation of the RX DQS-Gating training for the PHY, the uses needs to set the  reg_ddrc_auto_ref_dis set to 1 to disable the auto refresh function and wait for this register change to 0x1. Then enable the RX DQS-Gating training.
                                                                * Default Vale : 0x1  */
            __IM uint32_t rank1_auto_ref_cs_to_reg : 4;                    /* bit[7,4].  The auto refresh state of the rank1.
                                                                * When rank1_auto_ref_cs_to_reg = 4'h1, it means the auto refresh state machine is in idle state.
                                                                * If the user uses the reg_ddrc_auto_ref_dis set to 1 to disable the auto refresh function, it should wait for this register change to 4'h1 to excute the next step. 
                                                                * eg. If the user needs to close the auto-refresh operation of the RX DQS-Gating training for the PHY, the uses needs to set the  reg_ddrc_auto_ref_dis set to 1 to disable the auto refresh function and wait for this register change to 0x1. Then enable the RX DQS-Gating training.
                                                                * Default Vale : 0x1  */
            __IM uint32_t rank2_auto_ref_cs_to_reg : 4;                    /* bit[11,8].  The auto refresh state of the rank2.
                                                                * When rank0_auto_ref_cs_to_reg = 4'h1, it means the auto refresh state machine is in idle state.
                                                                * If the user uses the reg_ddrc_auto_ref_dis set to 1 to disable the auto refresh function, it should wait for this register change to 4'h1 to excute the next step. 
                                                                * eg. If the user needs to close the auto-refresh operation of the RX DQS-Gating training for the PHY, the uses needs to set the  reg_ddrc_auto_ref_dis set to 1 to disable the auto refresh function and wait for this register change to 0x1. Then enable the RX DQS-Gating training.
                                                                * Default Vale : 0x0  */
            __IM uint32_t rank3_auto_ref_cs_to_reg : 4;                    /* bit[15,12].  The auto refresh state of the rank3.
                                                                * When rank1_auto_ref_cs_to_reg = 4'h1, it means the auto refresh state machine is in idle state.
                                                                * If the user uses the reg_ddrc_auto_ref_dis set to 1 to disable the auto refresh function, it should wait for this register change to 4'h1 to excute the next step. 
                                                                * eg. If the user needs to close the auto-refresh operation of the RX DQS-Gating training for the PHY, the uses needs to set the  reg_ddrc_auto_ref_dis set to 1 to disable the auto refresh function and wait for this register change to 0x1. Then enable the RX DQS-Gating training.
                                                                * Default Vale : 0x0  */
                uint32_t  : 16;
        } reg_0x4fc_b;
    };

    union {
        __IOM uint32_t reg_0x500;
        struct {
            __IOM uint32_t reg_wcmd_pend_to_starve_max_time : 13;                    /* bit[19,7].  The register used to control the initial value of the read command pending state in the read command queue.
                                                                * When the read command store in the command queue, the read command will have a pending initial value and load to the counter. The counter will be decreased until this read command is scheduled. When this counter is decreaed to 8'h0, this pending read command will be in the starve state and has the highest priority.
                                                                * Default Vale : 0x1fff  */
            __IOM uint32_t reg_wcmd_pend_to_starve_flag_en : 1;                    /* bit[20].  The enable signal of the read command starve function in the read command queue. Active High.
                                                                * 1: The read command which is pending in the read command queue will be go into the starve state when the starve conter is decreased to 8'h0.
                                                                * 0: Disable the starve function of the read commands which are in the command queue.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_vpw_time_out_init_value : 11;                    /* bit[31,21].  The register used to control the initial value of the read variable priority command waiting initial value in the axi slave command queue. When the read variable priority command is stored in the command queue, the commad will have a waiting intial value and load to the counter. This counter will follow the read command and stored in the command queue in the core. The read variable priority command will change to highest priority command when the counter changes to 6'h0.
                                                                * Default Vale : 0x7ff  */
        } reg_0x500_b;
    };

    __IOM uint32_t reg_0x504;                /* This register is used to control the zqcalib command interval after enable the zqcalib function by set the reg_ddrc_zqcal_dis to 1'b0.
                                                                * time_unit = dfi_clk1x * 32.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x508;                /* Reserved.
                                                                * Default Vale : 0x0  */

    union {
        __IOM uint32_t reg_0x50c;
        struct {
            __IOM uint32_t reg_ddrc_tzqlat_ctrl : 8;                    /* bit[7,0].  This register used to control the timing parameter between the zqcalib command to any other command.
                                                                * time_unit = dfi_clk1x.
                                                                * Default Vale : 0x0  */
                uint32_t  : 23;
            __IOM uint32_t reg_ddrc_zqcal_dis : 1;                    /* bit[31].  The disable signal of the function which periodly generate the ZQ CALIBRATION command to calibrate DRAM Ron and ODT values.
                                                                * Default Vale : 0x1  */
        } reg_0x50c_b;
    };

    union {
        __IOM uint32_t reg_0x510;
        struct {
            __IOM uint32_t reg_ddrc_wc_nums : 8;                    /* bit[7,0].  The register used to control the max write combine numbers after enable the write combine function.
                                                                * When the write combine numbers arrive the max number, the controller will stop to accept the same address write command when there is the pending same write address command in the queue.
                                                                * Default Vale : 0xff  */
            __IOM uint32_t reg_ddrc_wc_dis : 1;                    /* bit[8].  The write combine function disable signal. Active High.
                                                                * 1: Disable the write combine function.
                                                                * 0: Enable the write combine function. The controller will combine the pending same address write command to one command to improve the bandwidth especially for narrow transfer.
                                                                * Default Vale : 0x0  */
                uint32_t  : 7;
            __IOM uint32_t reg_scram_en : 1;                    /* bit[16].  The data scram enable signal. Active High.
                                                                * When enable this function, the write data will base on the reg_scram_seed* to do the encode scram and decode scram.
                                                                * Default Vale : 0x0  */
                uint32_t  : 15;
        } reg_0x510_b;
    };

    __IOM uint32_t reg_0x514;                /* The bit[31:0] of the scam random seed.
                                                                * Default Vale : 0x11111111  */

    __IOM uint32_t reg_0x518;                /* The bit[63:32] of the scam random seed.
                                                                * Default Vale : 0x22222222  */

    __IOM uint32_t reg_0x51c;                /* The bit[95:64] of the scam random seed.
                                                                * Default Vale : 0x33333333  */

    __IOM uint32_t reg_0x520;                /* The bit[127:96] of the scam random seed.
                                                                * Default Vale : 0x44444444  */

    __IOM uint32_t reg_0x524;                /* Choose the MPR(Multi Purpose Register) mode signal.
                                                                * 0: MPR read mode.
                                                                * 1: MPR write mode.
                                                                * For DDR4, only page0 (reg_mpr_page=2'b00) support MPR write, all of four pages support MPR read.
                                                                * For DDR3, just support MPR read, do not support MPR write, and only has one page.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x528;                /* Choose the MPR operation (OP) mode for one page.
                                                                * 0: single MPR read or write, read or write single location in one page.
                                                                * 1: successive MPR read or write, read or write all 4 locations in one page.
                                                                * For DDR4, two mode all support.
                                                                * For DDR3, only support single MPR OP mode,because DDR3 choose location when MRS command.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x52c;                /* Choose MPR page. 
                                                                * For DDR4, total 4 pages. 2'b00: page0;   2'b01: page1;   2'b10: page2;   2'b11: page3.
                                                                * For DDR3, only 1 page. This signal do not care.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x530;                /* For DDR4, choose MPR read format which decide the format of MPR back data.
                                                                * 2'b00: serial return.
                                                                * 2'b01: parallel return.
                                                                * 2'b10: staggered return.
                                                                * 2'b11: do not care.
                                                                * For DDR3, do not care.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x534;                /* Choose which rank to do MPR OP. 4'b0001,4'b0010,4'b0100,4'b1000 represent rank0-rank3. 
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x538;                /* Choose the location of MPR page.
                                                                * For DDR4, total 4 locations per page, this signal will be mapped to [BA1:BA0] under MPR read or write command. The register do not care when reg_mpr_page_op_mode=1'b1.
                                                                * For DDR3,total 4 locations for the only page, this signal will be mapped to [A1:A0] under MPR MRS command.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x53c;                /* Enable the MPR function when related mode registers have been configed, active high.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x540;                /* The value to MPR when MPR write command.
                                                                * when reg_mpr_page_op_mode = 1'b0; [7:0] valid.
                                                                * when reg_mpr_page_op_mode = 1'b1; [31:0] valid. mapping to 4 locations in one page, one location take 8 bit.
                                                                * Default Vale : 0x0  */

    __IM uint32_t reg_0x544;                /* The read back value when MPR read command. 
                                                                * when reg_mpr_page_op_mode=1'b0, reg_mpr_rd_data[7:0] is the back data from the given mpr location.
                                                                * when reg_mpr_page_op_mode=1'b1, reg_mpr_rd_data[31:0] is the back data from 4 mpr locations in one page.
                                                                * Default Vale : 0x0  */

    union {
        __IM uint32_t reg_0x548;
        struct {
            __IM uint32_t reg_mpr_op_done : 1;                    /* bit[0].  The signal to represent MPR OP done. reg_mpr_en can be low when the register high.
                                                                * Default Vale : 0x0  */
            __IM uint32_t reg_mpr_rd_data_valid : 1;                    /* bit[1].  The signal to represent MPR read back data valid,  when reg_mpr_rd_data_valid=1'b1, reg_mpr_rd_datan is valid.
                                                                * Default Vale : 0x0  */
                uint32_t  : 6;
            __IM uint32_t waddr_in_out_of_range_to_reg : 8;                    /* bit[15,8].  The interrupt signal of the waddr range exceed the setting density by the reg_sdram_*_size. Active High.
                                                                * Default Vale : 0x0  */
            __IM uint32_t raddr_in_out_of_range_to_reg : 8;                    /* bit[23,16].  The interrupt signal of the waddr range exceed the setting density by the reg_sdram_*_size. Active High.
                                                                * Default Vale : 0x0  */
                uint32_t  : 8;
        } reg_0x548_b;
    };

    union {
        __IOM uint32_t reg_0x54c;
        struct {
            __IOM uint32_t reg_ddrc_wrcam_lowthresh : 6;                    /* bit[5,0].  Reserved.
                                                                * Default Vale : 0x8  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_wrcam_highthresh : 6;                    /* bit[13,8].  Reserved.
                                                                * Default Vale : 0x2  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_rd_pghit_num_thresh : 6;                    /* bit[21,16].  used to set read page-hit threshold. when page-hit cell numbers in read comand queue reach the threshold, the read state gets higher priority, write state will switch to read state immediately.
                                                                * Default Vale : 0x4  */
                uint32_t  : 2;
            __IOM uint32_t reg_ddrc_wr_pghit_num_thresh : 6;                    /* bit[29,24].  used to set write page-hit threshold. when page-hit cell numbers in write comand queue reach the threshold, the write state gets higher priority, read state will switch to write state immediately.
                                                                * Default Vale : 0x4  */
                uint32_t  : 2;
        } reg_0x54c_b;
    };

    union {
        __IOM uint32_t reg_0x550;
        struct {
            __IOM uint32_t reg_ddrc_rd_act_idle_gap : 8;                    /* bit[7,0].  Reserved.
                                                                * Default Vale : 0x10  */
            __IOM uint32_t reg_ddrc_wr_act_idle_gap : 8;                    /* bit[15,8].  Reserved.
                                                                * Default Vale : 0x8  */
            __IOM uint32_t reg_ddrc_rd_page_exp_cycles : 8;                    /* bit[23,16].  Reserved.
                                                                * Default Vale : 0x3c  */
            __IOM uint32_t reg_ddrc_wr_page_exp_cycles : 8;                    /* bit[31,24].  Reserved.
                                                                * Default Vale : 0x8  */
        } reg_0x550_b;
    };

    union {
        __IOM uint32_t reg_0x554;
        struct {
            __IOM uint32_t reg_ddrc_rdwr_switch_policy_sel : 1;                    /* bit[0].  Reserved.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_opt_wrcam_fill_level : 1;                    /* bit[1].  Reserved.
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_ddrc_dis_speculative_act : 1;                    /* bit[2].  Reserved.
                                                                * Default Vale : 0x1  */
                uint32_t  : 5;
            __IOM uint32_t reg_ddrc_delay_switch_write : 4;                    /* bit[11,8].  Reserved.
                                                                * Default Vale : 0x2  */
                uint32_t  : 20;
        } reg_0x554_b;
    };

    union {
        __IOM uint32_t reg_0x558;
        struct {
            __IOM uint32_t reg_ddrc_trd2wr : 8;                    /* bit[7,0].  Reserved.
                                                                * Default Vale : 0x1f  */
            __IOM uint32_t reg_ddrc_twr2rd : 8;                    /* bit[15,8].  Reserved.
                                                                * Default Vale : 0x1f  */
            __IOM uint32_t reg_gs_rdwr_idle_gap : 8;                    /* bit[23,16].  Reserved.
                                                                * Default Vale : 0x0  */
                uint32_t  : 7;
            __IOM uint32_t reg_ddrc_user_cmd_valid : 1;                    /* bit[31].  Reserved.
                                                                * Default Vale : 0x0  */
        } reg_0x558_b;
    };

    __IOM uint32_t reg_0x55c;                /* Reserved.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x560;                /* Reserved.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x564;                /* Reserved.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x568;                /* Reserved.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x56c;                /* The data bitnum in ecc poison. Inject the error in burst0 byte0123 of read data. 
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x570;                /* The data bitnum in ecc poison. Inject the error in burst0 byte4567 of read data.  
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x574;                /* The data bitnum in ecc poison. Inject the error in burst1 byte0123 of read data. 
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x578;                /* The data bitnum in ecc poison. Inject the error in burst1 byte4567 of read data. 
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x57c;                /* The data bitnum in ecc poison. Inject the error in burst2 byte0123 of read data. 
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x580;                /* The data bitnum in ecc poison. Inject the error in burst2 byte4567 of read data. 
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x584;                /* The data bitnum in ecc poison. Inject the error in burst3 byte0123 of read data. 
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x588;                /* The data bitnum in ecc poison. Inject the error in burst3 byte4567 of read data.  
                                                                * Default Vale : 0x0  */

    union {
        __IOM uint32_t reg_0x58c;
        struct {
            __IOM uint32_t reg_ddrc_ecc_poison_bit_num_burst3_byte_ecc : 8;                    /* bit[7,0].  The data bitnum in ecc poison. Inject the error in burst3 of read data.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_ecc_poison_bit_num_burst2_byte_ecc : 8;                    /* bit[15,8].  The data bitnum in ecc poison. Inject the error in burst2 of read data.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_ecc_poison_bit_num_burst1_byte_ecc : 8;                    /* bit[23,16].  The data bitnum in ecc poison. Inject the error in burst1 of read data.
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_ecc_poison_bit_num_burst0_byte_ecc : 8;                    /* bit[31,24].  The data bitnum in ecc poison. Inject the error in burst0 of read data.
                                                                * Default Vale : 0x0  */
        } reg_0x58c_b;
    };

    __IOM uint32_t reg_0x590;                /* The partal scrub start adress. When enable the partal scrub function, the controller will generate the partal scrub address from the start address.
                                                                * Default Vale : 0x0  */

    __IOM uint32_t reg_0x594;                /* The partal scrub end adress. When enable the partal scrub function, the controller will generate the partal scrub address to the end address and repeat from the start address.
                                                                * Default Vale : 0x1fff0  */

    __IOM uint32_t reg_0x598;                /* "The interval used to control the interval between the two period scrub command. The register value is valid when the reg_ddrc_partal_scrub_en set to 1.
                                                                * Interval value = register_value * 1024 * core_clk. "
                                                                * Default Vale : 0x3f  */

    union {
        __IOM uint32_t reg_0x59c;
        struct {
            __IOM uint32_t reg_ddrc_partal_scrub_en : 1;                    /* bit[0].  enable the partal function. Active high
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_ddrc_dis_scrub_cmd_scrub : 1;                    /* bit[1].  enable the scrub cmd access to scrub. Active high
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_init_clk_cg_en : 1;                    /* bit[2].  enable initialization function clk gate. Low meas turn off the clk
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_effi_clk_cg_en : 1;                    /* bit[3].  enable efficiency calculation function clk gate. Low meas turn off the clk
                                                                * Default Vale : 0x0  */
            __IOM uint32_t reg_load_mode_cg_en : 1;                    /* bit[4].  enbale user load mode function clk gate. Low meas turn off the clk  
                                                                * Default Vale : 0x1  */
            __IOM uint32_t reg_bist_cg_en : 1;                    /* bit[5].  enable membist function clk gate. Low meas turn off the clk
                                                                * Default Vale : 0x0  */
                uint32_t  : 26;
        } reg_0x59c_b;
    };
            
    
} DDR_CTRL_Type;



#endif

#endif

